本研究論文提出一個十位元低電壓及高能源效率的混合型連續近似(SAR)類比數位轉換器(ADC)，可以應用於無線感測網絡的系統中。其操作在超低電壓的0.4伏特至0.7伏特，以維持良好的功率消耗表現，並可適用於不同頻段以配合各種應用需求。
所提出的混合型類比數位轉換器，在架構方面包含了粗調轉換器(Coarse ADC)以及細調轉換器(Fine ADC)，分別操作在電壓域以及時間域。粗調轉換器的部分使用7位元的VCM-based連續近似類比數位轉換器，此架構有較低的數位類比轉換器(DAC)切換功率消耗，並可以維持固定的共模準位電壓。轉換結束後的殘餘電壓在細調轉換部分會藉電壓控制延遲電路(VCDL)將電壓轉換至時間域，再利用Vernier 延遲架構的時間數位轉換器將其量化為3.5位元的編碼。其中額外的0.5位元為冗位元，可以藉此放寬粗調轉換器的需求並且容忍二個轉換器之間的偏移不匹配。此架構可以減少四倍的數位類比轉換器單位電容使用數量，以及放寬粗調轉換器的需求，使得比較器對於雜訊的需求降低，大幅減少其功率消耗。
此架構使用90奈米1P9M互補式金氧半導體製程製作，晶片總面積為1000×1000μm2，核心電路面積為120×340μm2，在0.4至0.7伏電源電壓及相對應的250千至4百萬取樣頻率操作時，以及在Nyquist輸入訊號頻率下，此晶片實現SNDR從53.7至54.8dB，其對應的ENOB為8.63至8.81，功率消耗為0.2至8.3微瓦，等效的figure of merit (FoM)為2.02至5.16fJ/conversion-step。

This thesis presents an ultra-low voltage and power efficient 10-bit hybrid
successive-approximation register (SAR) analog-to-digital converter (ADC) for wireless sensor
network.
The proposed ADC operates at ultra-low supply voltage from 0.4V to 0.7V to save power
consumption. The hybrid architecture is proposed to reduce the total amount of capacitance and
relieve requirement of comparator, and the ADC is composed of coarse and fine conversions by 7-bit
SAR ADC and 3.5-bit time-domain quantizer, respectively. Using residue voltages generated by
coarse ADC and converting it to time-domain, the fine ADC detects the least three bits with 0.5-bit
redundancy by Vernier delay structure.
The prototype was fabricated using 90nm 1P9M CMOS technology and core area is only
120×340μm2. At 0.4-to-0.7V supply and 250KS/s-to-4MS/s sampling rate, the ADC achieves SNDR
from 53.7 to 54.8dB corresponding ENOB from 8.63 to 8.81 at Nyquist-rate input and consumes
0.2-to-9.3 W power consumption, resulting in a figure of merit (FOM) from 2.02-to 5.16 fJ
/conversion-step.

Abstract
Content
List of Figures
List of Tables
1. Introduction
1.1 Motivation
1.2 Performance Metrics of SAR ADC
1.2.1 Resolution
1.2.2 Nyquist Criterion
1.2.3 Quantization Error
1.2.4 Differential Nonlinearity (DNL)
1.2.5 Integral Nonlinearity (INL)
1.2.6 Offset and Gain error
1.2.7 SNDR and SFDR
1.2.8 Effective Number of Bit (ENOB)
1.2.9 Figure of Merit FoM
1.3 State of Arts
1.4 Target Specification
1.5 Thesis Organization
2. Successive Approximation Register ADC Overview
2.1 Introduction
2.2 Operation Procedure of Conventional SAR ADC
2.3 Consideration of Sample and Hold
2.3.1 On-Resistance of MOS Switches
2.3.2 Charge Injection
2.3.3 Clock Feedthrough
2.3.4 KT/C noise
2.3.5 Aperture Uncertainty
2.4 Consideration of Capacitive DAC
2.4.1 DAC Parasitic Capacitance
2.4.2 DAC Capacitor Mismatch
2.4.3 Settling Time
2.5 Consideration of Comparator
2.5.1 Comparator Input Offset
2.5.2 Kickback Noise
2.5.3 Input referred noise
2.6 SAR Logic
2.6.1 Asynchronous SAR Logic
2.7 Consideration of Voltage to Time Converter (VTC)
2.7.1 Linearity
2.7.2 VTC Timing Error
2.7.3 VTC Input Referred Noise
2.8 Consideration of Time to Digital Converter (TDC)
2.8.1 TDC Time Resolution and Number of Bit
2.8.2 TDC Delay Chain Offset
2.9 Summary
3. Hybrid Successive Approximation Register ADC
3.1 Introduction
3.2 Hybrid Successive Approximation Register ADC
3.2.1 Proposed Hybrid SA ADC structure
3.2.2 Hybrid SAR ADC Optimization of Stage Resolutions
3.3 Successive Approximation ADC
3.3.1 DAC Switching Methods
3.3.2 Topologies of Sample and Hold
3.3.3 Topologies of Comparator
3.3.4 Digital SAR Control Logic
3.4 Time domain quantizer
3.4.1 Topologies of Voltage to Time Converter
.3.4.2 Topologies of Time to Digital Converter
3.5 Summary
4. Circuit Implementation of Successive Approximation ADC
4.1 Introduction
4.2 Inter-stage consideration of Hybrid SAR ADC
4.2.1 Linearity of VTC
4.2.2 Offset mismatch
4.2.3 Noise
4.3 Analog Building Blocks
4.3.1 Design of Sample and Hold
4.3.2 Design of Comparator and Calibration
4.3.3 Design of VTC and Calibration
4.4 Digital Building Blocks
4.4.1 Design of TDC and Delay Time Locking Procedure
4.4.2 Digital Control Logic
4.4.3 Calibration Flow Design
4.5 Pre-Layout and Post-Layout Simulation
4.6 Summary
5. Measurement Result
5.1 Introduction
5.2 Measurement Environment Setup
5.3 Measurement Parameter Setup
5.4 Static Performance
5.5 Dynamic Performance
5.6 Performance Summary and Comparison
5.7 Summary
6. Conclusion and Future Work
6.1 Conclusion
6.2 Future Work
Bibliography

[1] P. Harpe, et al., "A 10b/12b 40 kS/s SAR ADC With Data-Driven Noise Reduction Achieving up to 10.1b ENOB at 2.2 fJ/Conversion-Step," IEEE J. Solid-State Circuits, vol.48, no.12, pp. 3011-3018, Dec. 2013.
[2] M. Ahmadi, et al., "A 3.3fJ/conversion-step 250kS/s 10b SAR ADC using optimized vote allocation," IEEE CICC , pp. 22-25 Sept. 2013.
[3] P. Harpe, et al., "An oversampled 12/14b SAR ADC with noise reduction and linearity enhancements achieving up to 79.1dB SNDR," IEEE ISSCC Dig. Tech. Papers, pp. 194-195, Feb. 2014.
[4] V. Giannini, et al., "An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS," IEEE ISSCC Dig. Tech. Papers, pp. 238-239,610, Feb. 2008.
[5] P. Harpe, et al., "A 7-to-10b 0-to-4MS/s flexible SAR ADC with 6.5-to-16fJ/ conversion-step," IEEE ISSCC Dig. Tech. Papers, pp. 472-474, Feb. 2012.
[6] H.-Y. Tai, et al., "11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS," IEEE ISSCC Dig. Tech. Papers, pp. 196-197, Feb. 2014.
[7] C.-Y. Liou, C.-C. Hsieh, "A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with charge-average switching DAC in 90nm CMOS," IEEE ISSCC Dig. Tech. Papers, pp. 280-282, Feb. 2013.
[8] H.-Y. Huang, et al., "A 9.2b 47fJ/conversion-step asynchronous SAR ADC with input range prediction DAC switching," IEEE ISCAS, pp. 2353-2356, May 2012.
[9] Chun-Cheng Liu; Soon-Jyh Chang; Guan-Ying Huang; Ying-Zu Lin, "A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure," IEEE J. Solid-State Circuits, vol.45, no.4, pp. 731-740, April 2010.
[10] Y. Zhu, et al., "A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS," IEEE J. Solid-State Circuits, vol.45, no.6, pp. 1111-1121, June 2010.
[11] Z. Zhu, et al., "VCM-based monotonic capacitor switching scheme for SAR ADC," Electronics Letters , vol.49, no.5, pp. 327-329, Feb. 2013.
[12] G.-Y. Huang, et al., "A 1-μW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications," IEEE J. Solid-State Circuits, vol.47, no.11, pp. 2783-2795, Nov. 2012.
[13] F.M. Yaul, et al., "11.3 A 10b 0.6nW SAR ADC with data-dependent energy savings using LSB-first successive approximation," IEEE ISSCC Dig. Tech. Papers, pp.198-199, Feb. 2014.
[14] B. Murmann, "ADC Performance Survey 1997-2014," [Online]. Available: http://web.stanford.edu/~murmann/adcsurvey.html.
[15] H.-J. Jeon, et al., "Offset voltage analysis of dynamic latched comparator," IEEE MWSCAS, pp. 1-4, Aug. 2011.
[16] H. Jun, et al., "Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparators," IEEE TCASI, vol.56, no.5, pp. 911-919, May 2009.
[17] A. Nikoozadeh, et al., "An Analysis of Latch Comparator Offset Due to Load Capacitor Mismatch," IEEE TCASII, vol.53, no.12, pp. 1398-1402, Dec. 2006.
[18] P.M. Figueiredo, et al., "Kickback noise reduction techniques for CMOS latched comparators," IEEE TCASII, vol.53, no.7, pp. 541-545, July 2006.
[19] P. Nuzzo, et al., "Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures," IEEE TCASI, vol.55, no.6, pp.1441-1454, July 2008.
[20] M. Alioto, et al., "Power–Delay–Area–Noise Margin Tradeoffs in Positive-Feedback MOS Current-Mode Logic," IEEE TCASI, vol.54, no.9, pp. 1916-1928, Sept. 2007.
[21] H. Pekau, et al., "A CMOS integrated linear voltage-to-pulse-delay-time converter for time based analog-to-digital converters," IEEE ISCAS, pp. 2373-2376, May 2006.
[22] S.-K. Lee et al., "A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface," IEEE J. Solid-State Circuits, vol.46, no.3, pp. 651-659, March 2011.
[23] G.W. Roberts, et al., "A Brief Introduction to Time-to-Digital and Digital-to-Time Converters," IEEE TCASII, vol.57, no.3, pp. 153-157, March 2010.
[24] J.-P. Jansson, et al., "A CMOS time-to-digital converter with better than 10 ps single-shot precision," IEEE J. Solid-State Circuits, vol.41, no.6, pp. 1286-1296, June 2006.
[25] Y.-Z. Lin et al., "A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS," IEEE TCASI, vol.60, no.3, pp. 570-581, March 2013.
[26] C.C. Lee, et al., "A SAR-Assisted Two-Stage Pipeline ADC," IEEE J. Solid-State Circuits, vol.46, no.4, pp. 859-869, April 2011.
[27] F. van der Goes, et al., "A 1.5mW 68dB SNDR 80MS/s 2× interleaved SAR-assisted pipelined ADC in 28nm CMOS," IEEE ISSCC Dig. Tech. Papers, vol., no., pp. 200-201, Feb. 2014.
[28] J. Fredenburg, et al., "A 90MS/s 11MHz bandwidth 62dB SNDR noise-shaping SAR ADC," IEEE ISSCC Dig. Tech. Papers, pp. 468-470, Feb. 2012
[29] A. Shikata, et al.,"A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS," IEEE J. Solid-State Circuits, vol.47, no.4, pp. 1022-1030, April 2012.
[30] J. Guerber, et al., "A 10-b Ternary SAR ADC With Quantization Time Information Utilization," IEEE J. Solid-State Circuits, vol.47, no.11, pp. 2604-2613, Nov. 2012.
[31] Y. Zhu, et al., "A voltage feedback charge compensation technique for split DAC architecture in SAR ADCs," IEEE ISCAS, pp. 4061-4064, May 2010.
[32] S. Lei, et al., "Analysis on Capacitor Mismatch and Parasitic Capacitors Effect of Improved Segmented-Capacitor Array in SAR ADC," IEEE IITA, vol.2, pp. 280-283, Nov. 2009.
[33] Z. Dai, et al., "A 3-nW 9.1-ENOB SAR ADC at 0.7 V and 1 kS/s," IEEE ESSCIRC, pp. 369-372, Sept. 2012.
[34] R. Sekimoto, et al., "A 0.5-V 5.2-fJ/Conversion-Step Full Asynchronous SAR ADC With Leakage Power Reduction Down to 650 pW by Boosted Self-Power Gating in 40-nm CMOS," IEEE J. Solid-State Circuits, vol.48, no.11, pp. 2628-2636, Nov. 2013
[35] J.-H. Tsai, et al., "A 1-V, 8b, 40MS/s, 113μW charge-recycling SAR ADC with a 14μW asynchronous controller," IEEE Symp. VLSI Circuits Dig. Tech. Papers, pp. 264-265, June 2011.
[36] B.P. Ginsburg, et al., "Dual Time-Interleaved Successive Approximation Register ADCs for an Ultra-Wideband Receiver," IEEE J. Solid-State Circuits, vol.42, no.2, pp. 247-257, Feb. 2007.
[37] A. Agnes, et al., "A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC with Time-Domain Comparator," IEEE ISSCC Dig. Tech. Papers, pp. 246-247, Feb. 2008.
[38] J.-Y. Um et al., "A Digital-Domain Calibration of Split-Capacitor DAC for a Differential SAR ADC without Additional Analog Circuits," IEEE TCASI, vol.60, no.11, pp. 2845-2856, Nov. 2013.
[39] M. Wiessflecker, et al., "An 11 bit SAR ADC combining a split capacitor array with a resistive ladder and a configurable noise time domain comparator," IEEE MWSCAS, pp.101-104, Aug. 2012.
[40] Y. Jianjun, et al., "A 12-Bit Vernier Ring Time-to-Digital Converter in 0.13 CMOS Technology," IEEE J. Solid-State Circuits, vol.45, no.4, pp. 830-842, April 2010.
[41] B. Mesgarzadeh, et al., "A Low-Power Digital DLL-Based Clock Generator in Open-Loop Mode," IEEE J. Solid-State Circuits, vol.44, no.7, pp.1907-1913, July 2009.
[42] R.-J. Yang, et al., "A 40–550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm," IEEE J. Solid-State Circuits, vol.42, no.2, pp.361-373, Feb. 2007.
[43] A. Abidi, "Phase Noise and Jitter in CMOS Ring Oscillators," IEEE J. Solid-State Circuits, vol.41, no.8, pp. 1803-1816, Aug. 2006.
[44] A. Homayoun, et al., "Relation between Delay Line Phase Noise and Ring Oscillator Phase Noise," IEEE J. Solid-State Circuits, vol.49, no.2, pp.384-391, Feb. 2014.
[45] C.-H. Chan, et al., "A voltage-controlled capacitance offset calibration technique for high resolution dynamic comparator," IEEE ISOCC, pp.392-395, Nov. 2009.
[46] M. Miyahara, et al., "A low-noise self-calibrating dynamic comparator for high-speed ADCs," IEEE ASSCC, pp.269-272, Nov. 2008.
[47] J. Lu, et al., "A Low-Power High-Precision Comparator With Time-Domain Bulk-Tuned Offset Cancellation,"IEEE TCASI, vol.60, no.5, pp.1158-1167, May 2013.
[48] D.-G. Chen, et al., "A low-power dynamic comparator with digital calibration for reduced offset mismatch," IEEE ISCAS, pp.1283-1286, May 2012.
[49] P.-L. Chen, et al., "A portable digitally controlled oscillator using novel varactors," IEEE TCASII, vol.52, no.5, pp. 233-237, May 2005.
[50] M. Maymandi-Nejad, et al., "A monotonic digitally controlled delay element," IEEE J. Solid-State Circuits, vol.40, no.11, pp. 2212-2219, Nov. 2005.
[51] P. Raha, et al., "A robust digital delay line architecture in a 0.13 μm CMOS technology node for reduced design and process sensitivities," IEEE Symp. QED, pp. 148-153, 2002.