本論文主要為探討碳化矽垂直型雙佈植金氧半場效電晶體的設計與製作，採用一個新穎的離子佈植遮罩以擺脫舊有作法的金屬遮罩。新的製程由於除去了金屬汙染的風險，讓製程得以與業界的金氧半場效電晶體銜接。綜合自我對準氧化製程與歐姆金屬自我對準製程，可以縮小元件的單元線寬，因此可期達到有效降低特徵導通電阻的目的。 本次實驗量測到的最佳特徵導通電阻為85 mΩ*cm2，閘極電壓為20伏特、汲極電壓為1伏特，發生在有效通道寬度最大的元件與動作區面積最小的元件，元件JFET長度皆為5 μm。本次實驗量測到的最佳崩潰電壓為2240伏特，為厚度為30 μm的漂移區，崩潰電壓為理想崩潰電壓值的60%。由模擬可以得知，此結果是由於在1650℃熱退火活化不完全的影響，在該溫度只有約60%的活化率。

The thesis reports the design and fabrication of 4H-SiC double implant MOSFET with a novel ion implantation masking process, which gets rid of the metal mask in previous approaches. This new process is therefore compatible with industrial MOSFET process since it eliminates the risk of metal contamination. Combining the self-aligned oxidation process and the self-aligned ohmic contact process, the device cell pitch can be narrowed and hence the specific on resistance is expected to reduce significantly.
From the experiment results, the best RON,SP is 85 mΩ*cm2, extracted when Vg = 20 V, and Vd = 1 V on a device with the longest effective channel width and a device with the smallest active area, with the JFET length being 5 μm. The best breakdown voltage measured in this work is 2240 V for a 30 μm drift layer thickness, about 60% of the ideal breakdown voltage. From simulation results, it is attributed to the incomplete activation at 1650℃ anneal, which is estimated about 60% at that temperature.

中文摘要 I
Abstract II
圖目錄 V
表目錄 VIII
第一章 序論 1
1.1 寬能隙材料─4H-碳化矽 (4H-SiC) 1
1.2 垂直型雙佈植金氧半電晶體 2
1.3 文獻回顧 3
1.4 研究動機與論文大綱 4
第二章 元件設計與模擬 6
2. DMOSFET元件改善 6
2.1 通道電阻改善 6
2.1.1 自我對準氧化製程 7
2.1.2 氧化熱退火製程 7
2.2 JFET區域電阻改善 8
2.3 基極歐姆接觸佈局改善 8
2.4 歐姆接觸金屬自我對準製程 8
2.5 接面終端展延設計 9
2.6 新穎的離子佈植阻障層 10
2.7 DMOSFET元件模擬 11
第三章 製程實驗 18
3.1 一般清潔 (Normal cleaning) 18
3.2 P阱離子佈植 (P-well implant) 18
3.3 源極離子佈植 (Source implant) 19
3.4 基極離子佈植 (Body implant) 20
3.5 接面終端延展離子佈植 20
3.6 閘極氧化層成長 (Gate oxide formation) 21
3.7 閘極電極定義 (Gate electrode definition) 21
3.8 源極與基極歐姆接觸 22
3.9 汲極歐姆接觸與快速熱退火 23
3.10 源極墊金屬與閘極電極窗口打開 23
第四章 實驗量測結果與討論 34
4.1 基板濃度與測試元件 34
4.2 DMOSFET元件 36
第五章 結論與未來展望 54
參考文獻 55

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