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作者(中文):柯聖安
作者(外文):Ko, Sheng-An
論文名稱(中文):以標準CMOS製程實現1V輸入切換電容式升壓至3V到6V之神經刺激器
論文名稱(外文):A 1V Input, 3-to-6V Output, Switched-Capacitor Type Stimulator Using Standard CMOS Technology
指導教授(中文):黃柏鈞
指導教授(外文):Huang, Po-Chiun
口試委員(中文):吳介琮
李泰成
陳巍仁
蔡宗亨
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學號:100061574
出版年(民國):103
畢業學年度:102
語文別:中文
論文頁數:84
中文關鍵詞:功能性電刺激生醫植入式裝置神經刺激器升壓電路高電壓驅動器電路
外文關鍵詞:functional electrical stimulationbiomedical implantable deviceneuron stimulatorvoltage multiplierhigh voltage driver
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從已知的研究顯示,功能性電刺激可以用來治療許多的神經性疾病,如心律不整、感覺神經性耳聾、帕金森氏症等疾病,將輸入訊號刺激組織細胞進而調節神經細胞非正常的活動來治療疾病。在生醫植入式裝置中神經刺激器的設計考量中,為了達到有效的刺激效果,需要在電路中產生高電壓,並且一則考量電路的面積大小達到能夠整合於植入式裝置中,另一則考量電路的轉換效率達到有利於長時間的使用。
在本論文中,研究可以提供功能性電刺激的神經刺激器,其中包含升壓電路和高電壓驅動器電路。在升壓電路方面,提出新的混合式架構與分析其電路的數學模型。為了使電路在大範圍輸出電壓皆在高轉換效率的操作,提出切換級數的電路操作。進一步考量寄生電容對轉換效率的影響,提出輔助寄生提升路徑來達到提升整體電路轉換效率的電路技巧。利用混合式架構可以使用製程中不同種類的電容,將不同製造方式的電容整合在相同面積下達到面積最小化。使用0.18um標準CMOS製程的實驗結果顯示,升壓電路在負載電流為30uA-240uA的情況,可以將1V的輸入電壓達到3V-6V的輸出電壓。整體系統利用切換級數的操作可以在3V-6V的大範圍輸出電壓之中,達到轉換效率皆在48%-58%之間。在高電壓驅動器電路方面,改裝可以提供定電壓輸出的高電壓驅動器使其可以提供定電流的輸出。整合升壓電路和驅動器電路的模擬顯示,最高可以達到提供60us脈衝時間、120uA脈衝電流的功能性電刺激訊號。
Recent studies have shown that functional electrical stimulation can be used to treat neurological disorders, like cardiac dysrhythmia, sensorineural hearing loss, Parkinson's disease, and other diseases. A high voltage neuron stimulator is used in biomedical implantable devices. The chip size is considered to achieve an implantable device. High efficiency of the converter is also important to have long operating life.
In this thesis, a neuron stimulator, which provides a functional electrical stimulation, consists of a voltage multiplier and a high voltage driver circuit. A novel hybrid architecture is proposed and analyzed with a mathematical model. The circuit supplies a wide range output voltage of high efficiency with the proposed switching stages circuit operation. The hybrid architecture allows the use of different types of on chip capacitor to minimize the chip area. The proposed circuit technique of parasitic auxiliary path improves the efficiency of the whole circuit.
The voltage multiplier with 1V input can achieve 3V to 6V output voltage under the loading current from 30uA to 240uA using a standard 0.18um CMOS process technology. The measurement results demonstrate that the efficiency of the overall system reaches 48% to 58% over a wide range of output voltages. A constant voltage output circuit is transformed into a constant current output circuit. The simulation shows that the 60us pulse width and 120uA constant current functional electrical stimulation is provided by an integrated voltage multiplier and high voltage driver.
誌謝 i
摘要 ii
ABSTRACT iii
目錄 iv
圖目錄 vi
表目錄 ix
第一章 簡介 1
1.1 研究背景 1
1.2 原理介紹 2
1.2.1 神經元細胞與動作電位簡介 2
1.2.2 植入式生醫系統 5
1.2.3 神經刺激訊號簡介 7
1.3 研究動機 12
1.4 章節簡介 13
第二章 文獻回顧 14
2.1 高壓電路設計分析 15
2.1.1 電感式與電容式升壓電路 15
2.1.2 高壓可靠性分析 16
2.1.3 電容分析 18
2.2 切換式電容倍壓電路基本操作原理 21
2.2.1 電壓倍壓電路 21
2.2.2 推挽式架構(Push-pull Topology) 22
2.2.3 交叉耦合式架構(Cross-Coupled Topology) 24
2.3 升壓電路基本架構 25
2.3.1 Cockcroft-Walton 升壓電路 25
2.3.2 Dickson升壓電路 27
2.3.3 Serial-parallel升壓電路 29
2.3.4 效率分析與比較 30
2.4 切換式電容升壓電路現有技術回顧 31
第三章 電路實現 37
3.1 提出升壓電路架構 38
3.1.1 混合式升壓電路分析 38
3.1.2 提出升壓電路 40
3.2 效率分析 43
3.2.1 電荷泵使用級數 43
3.2.2 切換級數式技巧 48
3.2.3 輔助寄生提升路徑 49
3.3 電路實現 51
3.3.1 面積佈局規劃 51
3.3.2 交錯式相位 55
3.3.3 開關實現 56
3.3.4 回授路徑設計 57
3.4 架構比較與總結 58
第四章 電路量測 61
4.1 升壓電路電壓量測結果 62
4.2 升壓電路轉換效率量測結果 65
4.2.1 切換級數之效率量測結果 65
4.2.2 整體電路效率量測結果 66
4.3 晶片性能總結與比較 67
第五章 電流式高電壓驅動器電路 69
5.1 高電壓驅動器電路架構 71
5.1.1 高電壓驅動器電路實現 71
5.1.2 高電壓動態偏壓電路操作原理 72
5.2 電流刺激電路架構 74
5.3 模擬結果 76
5.3.1 單通道電流刺激器 76
5.3.2 雙通道電流刺激器 78
第六章 結論與未來工作 79
6.1 結論 79
6.2 未來工作 81
參考文獻 82
[1] A. M. Lozano, J. Dostrovsky, R. Chen, and P. Ashby, "Deep brain stimulation for Parkinson’s disease: disrupting the disruption," The Lancet Neurology, vol.1, pp. 225-231, 2002
[2] K. Nowak, E. Mix, J. Gimsa, U. Strauss, K. K. Sriperumbudur, R.Benecke, and U. Gimsa, “Optimizing a RodentModel of Parkinson's Disease for Exploring the Effects andMechanisms of Deep Brain Stimulation,” SAGE-Hindawi Access to Research Parkinson’s Disease, 414682(19pp), 2011
[3] K. D. Wise, D. J. Anderson, J. F. Hetke, D. R. Kipke, and K. Najafi,"Wireless implantable microsystems: High-density electronic interfaces to the nervous system," Proceedings of the IEEE, vol. 92, no. 1, pp. 76-97, 2004
[4] R. H. Olsson, and K. D. Wise, "A three-dimensional neural recording microsystem with implantable data compression circuitry," IEEE Journal of Solid-State Circuits, vol. 40, no. 12, pp. 2796-2804, 2005
[5] M. S. Chae, Z. Yang, M. R. Yuce, L. Hoang, and W. Liu, “A 128-Channel 6mW Wireless Neural Recording IC With Spike Feature Extraction and UWB Transmitter,” IEEE Neural System and Rehabilitation Engineering, vol. 17, no. 4, pp.312-320, 2009
[6] D. R. Merrill, “Electrical stimulation of excitable tissue: design of efficacious and safe protocols,” Journal of Neuroscience Methods, vol. 141, pp.171-198, 2005
[7] M.D. Hendelman, Walter; Skinner, R. Christopher; Humphreys, Peter, The Integrated Nervous System: A Systematic Diagnostic Approach, 1st ed. Published by CRC Press, 2009, Ch.1
[8] Stanley Gunstream, Anatomy & Physiology with Integrated Study Guide, 5th ed. Published by Pasadena City College, 2013, ch.8
[9] 王惠陽、廖國棟等人譯。1980。神經生理學。環球書社
[10] J. Vidal, and M. Ghovanloo "Towards a switched-capacitor based stimulator for efficient deep-brain stimulation," Proc. 32nd Annu. Int. Conf. IEEE Engineering in Medicine and Biology Society, pp.2927 -2930, 2010
[11] W. Franks, I. Schenker, P. Schmutz, and A. Hierlemann, “Impedance characterization and modeling of electrodes for biomedical applications,” IEEE Transactions on Biomedical Engineering , pp.1295-1302, 2005
[12] A.Merola, M. Zibetti, CA. Artusi, L. Rizzi, S. Angrisano, M. Lanotte, L. Lopiano, and MG. Rizzone, "80 Hz versus 130 Hz subthalamic nucleus deep brain stimulation: effects on involuntary movements," Parkinsonism Relat Disord. vol.19, Issue 4, pp.453-456, Apr. 2013
[13] M. Rizzone, M. Lanotte, B. Bergamasco, A. Tavella, E. Torre, G. Faccani, A. Melcarne, and L. Lopiano, "Deep brain stimulation of the subthalamic nucleus in Parkinson's disease: effects of variation in stimulation parameters," Journal of Neurol Neurosurg Psychiatry, pp.215-219, 2001
[14] C. H, “Gate oxide scaling limits and projection,” IEEE International Electron Devices Meeting, pp.319-322, Dec. 1994
[15] G. Groeseneken, R. Degraeve, T.Nigam, G. V. Den Bosch, H. E. Maes, “Hot carrier degradation and time-dependent dielectric breakdown in oxides,” Microelectronic Engineering, vol. 49, pp.27-40, 1999
[16] P. Y. Chiu, M. D. Ker, “Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuit,” Microelectronics Reliability, vol. 54, no. 1, pp. 64-70, Jan. 2014
[17] A. P. Grinberg, “History of the invention and development of accelerators (1922-1932),” Soviet Physics Uspekhi, vol. 18, no. 10, 1975
[18] J. S. Brugler, "Theoretical performance of voltage multiplier circuits," IEEE Journal of Solid-State Circuits, vol.6, no.3, pp. 132-135, Jun. 1971
[19] J. F. Dickson, “On-chip high voltage generation in MNOS integrated circuits using an improved voltage multiplier technique,” IEEE Journal of Solid-State Circuits, vol.11, no.3, pp. 374-378, Jun. 1976
[20] M. S. Makowski and D. Maksimovic, “Performance limits of switched-capacitor DC-DC converters,” IEEE Power Electronics Specialists Conference, vol. 2, Jun. 1995, pp. 1215–1221
[21] J. T. Wu and K. L. Chang, “MOS charge pumps for low-voltage operation,” IEEE Journal of Solid-State Circuits, vol.33, pp. 592-597, Apr. 1998
[22] M. D. Ker, S. L. Chen and C. S. Tsai, “design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes,” IEEE Journal of Solid-State Circuits, vol.41, pp. 1100-1107, May 2006
[23] R. Pelliconi, D. Iezzi, A.Baroni, M. Pasotti and P. Rolandi, “power efficient charge pump in deep submicron standard CMOS technology,” IEEE Journal of Solid-State Circuits, vol.38, pp. 1068-1071, Jun. 2003
[24] J. H. Tsai, C. Y. Tseng, W. K. Tseng, T. K. Shia and P. C. Huang “An integrated 12-V electret earphone driver with symmetric Cockcroft-Walton pumping topology for in-ear hearing aids,” IEEE Asian of Solid-State Circuits Conference, pp. 45-48, Nov. 2012
[25] H. P. Le, S. R. Sanders and E. Alon, “Design Techniques for Fully Integrated Switched-Capacitor DC-DC Converters,” IEEE Journal of Solid-State Circuits, vol.46, pp. 2120-2131, Sep. 2011
[26] R. Karadi and G. V. Pique, “3-Phase 6/1 Switched-Capacitor DC-DC Boost Converter Providing 16V at 7mA and 70.3% Efficiency in 1.1mm3,” IEEE International Solid-State Circuits Conference, pp.92-93, Feb. 2014
[27] A. Richelli, L. Mensi, L. Colalongo, P. L. Rolandi, and Zs. M. Kovacs-Vajna, “A 1.2-to-8V Charge-Pump with Improved Power Efficiency for Non-Volatille Memories,” IEEE International Solid-State Circuits Conference, pp.522-523, Feb. 2007
[28] A. Richelli, L. Colalongo, L. Mensi, A. Cacciatori, and Zs. M. Kovacs-Vajna, “Charge Pump Architectures Based on Dynamic Gate Control of the Pass-Transistors,” IEEE Transactions on Very Large Scale Integration Systems, vol. 17, no. 7, pp.964-967, July 2009
[29] R. Pelliconi, D. Iezzi, A. Baroni, M. Pasotti, and P. L. Rolandi, “Power Efficient Charge Pump in Deep Submicron Standard CMOS Technology,” IEEE Journal of Solid-State Circuits, vol. 38, no. 6, pp.1068-1071 Jun. 2003
[30] Y. C. Huang, M. D. Ker, and C. Y Lin, “Design of Negative High Voltage Generator for Biphasic Stimulator with SoC Integration Consideration,” IEEE Biomedical Circuits and Systems, pp. 28-30, Nov. 2012
[31] L. S. Y. Wong, S. Hossain, A. Ta, L. Weaver, C. Shaquer, A. Walker, J. Edvinsson, D. Rivas, H. Naas, A. Fawzi, A. Uhrenius, J.Lindberg, J. Johansson and P. Arvidsson, “A very low power CMOS mixed-signal IC for implantable pacemaker applications,” IEEE International Solid-State Circuits Conference, vol.1, pp. 318-530, Feb. 2004
[32] M. Sivaprakasam, W. Liu, M. S. Humayun, J. D. Weiland, ”A variable range bi-phasic current stimulus driver circuitry for an implantable retinal prosthetic device,” IEEE Journal of Solid-State Circuits, vol. 40, pp. 763-771, Mar. 2005
[33] X. Liu, A. Demosthenous and N. Donaldson, ” A Fully Integrated Fail-safe Stimulator Output Stage Dedicated to FES Stimulation,” IEEE International Symposium on Circuits and System, pp. 2076-2079, May 2007
[34] B. Serneels, T. Piessens, M. Steyaert and W. Dehaene, ” A high-voltage output driver in a standard 2.5 V 0.25 μm CMOS technology” IEEE International Solid-State Circuits Conference, vol.1, pp. 146-518, Feb. 2004
[35] X. Liu, A. Demosthenous and N. Donaldson, “A Dual-Mode Neural Stimulator Capable of Delivering Constant Current in Current-Mode and High Stimulus Charge in Semi-Voltage-Mode,” IEEE International Symposium on Circuits and System, pp. 2075-2078, May 2010
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