|
[1] E. Yaakobi, L. Grupp, P.H. Siegel, S. Swanson, and J.K.Wolf, "Character- ization and error-correcting codes for TLC ash memories" Proc. IEEE Int. Conf. Comput., Netw. Commun., Maui, HI, pp. 486-491, Jan-Feb. 2012. [2] W. Liu, J. Rho, and W. Sung, "Low-power high-throughput BCH error correction VLSI design for multi-level cell NAND ash memories" IEEE Workshop on Signal Processing Systems (SIPS), pp. 303-308, 2006. [3] R. Micheloni, R. Ravasio, A. Marelli, E. Alice, V. Altieri, A. Bovino, L. Crippa, E. D. Martino, L. D. Onofrio, A. Gambardella, E. Grillea, G. Guerra, D. Kim, C. Missiroli, I. Motta, A. Prisco, G. Ragone, M. Romano, M. Sangalli, P. Sauro, M. Scotti and S. Won, "A 4Gb 2b/cell NAND ash memory with embedded 5b BCH ECC for 36MB/s system read throughput" Proc. Intl Solid-State Circuits Conference, pp. 497- 506, Feb 2006. [4] F. Sun, S. Devarajan, K. Rose, and T. Zhang, "Design of On-Chip Error Correction Systems for Multilevel NOR and NAND Flash Memories" IET Circuits, Devices and Systems, Vol.1, No.3, pp.241-249, June 2007. [5] T.-H. Chen, Y.-Y. Hsiao, Y.-T. Hsing, and C.-W. Wu, "An adaptive-rate error correction scheme for NAND ash memory" Proc. IEEE VLSI Test Symp. (VTS), pp. 53-58, May 2009. [6] R. G. Gallager, "Low-density parity-check codes" IRE Trans. Inf. Theory, Vol. IT-8, pp. 21-28, Jan. 1962. [7] Digital Video Broadcasting (DVB); Second Generation Framing Struc- ture, Channel Coding and Modulation Systems for Broadcasting, Interac- tive Services, New Gathering and Other Broadband Satellite Applications 2004. [8] LDPC coding for OFDMA PHY. 802.16REVe Sponsor Ballot Recircula- tion Comment 2004, IEEE C802.16e-04/141r2. [9] Joint Proposal: High Throughput Extension to the 802.11 Standard: PHY. IEEE P802.11 Wireless LANs 2006, IEEE 802.11-05/1102r4. [10] Yeong-Luh Ueng, Jyun-Kai Hu, and Hsueh-Chih Chou, "Layered Decod- ing Architecture with Reduced Number of Hardware Buers for LDPC Codes". [11] Jyun-Kai Hu, "A Reduced-Complexity Layered Decoder Architecture for High-Rate QC-LDPC Codes" NTHU Master Thesis. [12] D. J. C. MacKay, "Good error-correcting codes based on very sparse ma- trices" IEEE Trans. Inf. Theory, Vol. 45, No. 2, pp. 399-431, Mar. 1999. [13] D. Hocevar, "A reduced complexity decoder architecture via layered de- coding of LDPC codes" 11. IEEE Workshop on Signal Processing Sys- tems, 2004, SIPS 2004, pp. 107-112, Oct. 2004. [14] M. M. Mansour and N. R. Shanbhag, "High-throughput LDPC decoders" IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, pp. 976996, Dec. 2003. [15] M. Fossorier, M. Mihaljevic, and H. Imai, "Reduced complexity iterative decoding of low-density parity-check codes based on belief propagation" IEEE Trans. Commum., vol. 47, no. 5, pp. 673-680, May 1999. [16] Chen, A. Dholakia, E. Eleftheriou, M. P. C. Fossorier, and X.-Y. Hu, "Reduced complexity decoding of LDPC codes" IEEE Trans. Commun., vol. 53, no. 8, pp. 1288-1299, Aug. 2005. [17] J. Chen and M. P. C. Fossorier, "Density evolution for two improved BP- based decoding algorithms of LDPC codes" IEEE Commum. Lett., vol. 6, pp.208-210, May 2002. [18] F. Guilloud, E. Boutillon, and J.L. Danger, "λ-Min Decoding Algorithm of Regular and Irregular LDPC Codes" In Proc. 3nd International Sym- posium on Turbo Codes & Related Topics, pages 451454, Brest, France, September 2003. [19] O. Daesun and K. Parhi, "Min-sum decoder architectures with reduced word length for LDPC codes" IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 1, pp. 105115, Jan. 2010. [20] Xiaofu Wu, Yue Song, Long Cui, Ming Jiang, and Chunming Zhao, "Adaptive-normalized min-sum algorithm" Future Computer and Com- munication (ICFCC), 2010 2nd International Conference, vol.2, pp.V2- 661-V2-663, 21-24 May 2010. [21] Chen, Rong, and Yi-ming Wang., "Modified Normalized Min-Sum decod- ing of LDPC codes" Signal Processing, 2008. ICSP 2008. 9th International Conference on. IEEE, 2008. [22] L. Hai-yang, Q. U. Wen-ze L.Bin, L. Jiang-peng,L.Shi-dong, and C. Jie, "Novel modified min-sum decoding algorithm for low-density paritycheck codes" The Journal of China Universities of Posts and Telecommunica- tions, vol. 17, pp. 1 -5, August 2010. [23] Valentin Savin, "Self-corrected min-sum decoding of LDPC codes" Proc. IEEE ISIT, pp. 146-150, Jul. 2008. [24] T. Mohsenin, D. Truong, and B. Baas, "A low-complexity message- passing algorithm for reduced routing congestion in LDPC decoders," IEEE Trans. Circuits Syst. I, vol. 57, no 5, pp. 1048-1061, May 2010. [25] A. Darabiha, A. C. Carusone, and F. R. Kschischang, "Power reduction techniques for LDPC decoders," IEEE J. Solid-State Circuits, vol. 43, no 8, pp. 1835-1845, Aug. 2008. [26] Kin-Chu Ho, Po-Chao Fang, Hsiang-Pang Li, C.-Y.M. Wang, and Hsie- Chia Chang. "A 45nm 6b/cell Charge-Trapping Flash Memory Using LDPC-Based ECC and Drift-Immune Soft-Sensing Engine" In Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE In- ternational, pages 222223, 2013. [27] H. Zhong, W. Xu, N. Xie, and T. Zhang, "Area-ecient min-sum decoder design for high-rate quasi-cyclic low-density parity-check codes in mag- netic reording" IEEE Trans. Magn., vol. 43, no. 12, pp. 41174122, Dec. 2007. [28] J. Kim, J. Cho, and W. Sung, "A high-speed layered min-sum LDPC decoder for error correction of NAND Flash memories" in Proc. IEEE Int. Midwest Symp. Circuits Syst., Aug. 2011, pp. 14. |