整合多片不同功能的裸晶於單一封裝基座的『三維晶片系統技術』擁有許多的優點，已被普遍認為是未來晶片設計、製造與封裝的主流趨勢。其中，以矽載板為中介層 (Interpose-Based) 的三維晶片系統被認為是介於傳統『裸晶間打線』為基礎的 SiP (System in Package)，和以『穿矽連接孔』的基礎的三維堆疊晶片的一個絕佳的折衷解決方案；非常適合許多低功耗、異質整合、且輕薄短小的可攜性產品。然而，以矽載板為中介層 (Interpose-Based) 的三維晶片系統的設計、測試、與診斷等各方面仍然存在許多的難題有待克服。
本篇論文解決在2.5-D堆疊IC中中介層連接線的測試和特性描述，這對良率改進和除錯是必要的。中介層連接線主要可能遭受到兩種參數性的故障影響－電阻性開路故障或橋接故障。不同於針對定值錯誤(stuck-at faults)，這些參數性故障並不會完全破壞中介層連接線的傳輸功能，但是會對中介層連接線的效能與品質造成影響。我們提出的方法提供一些超越過去在中介層連接線測試上的作品的特色。首先，我們的目標不僅是災難性的故障類型 (如固定型故障或嚴重的橋接故障)還有參數性的故障類型(包含電阻性開路故障和兩條中介層連接線間的電阻性橋接故障)。其次，我們的方法還可以用來預估每條無故障中介層連接線的傳播延遲。在測試時脈為10MHz，在32,768條中介層連接線的情況下需要 413ms的測試時間，而加入我們的DfT電路所增加的面積成本約為傳統測試方法的53.3%。

3D Integration that includes many dies on a single packaging substrate has been touted as a new trend for future integrated circuits. In addition to System-in-Package (SiP) and TSV-based stacked IC, the interposer-based 3D IC has been recently proposed by companies like TSMC as another cost-effective alternative. With many advantages like lower cost, ease-of-manufacturing, higher yield, etc., it could become an attractive solution for many portable devices that requires lower power, heterogeneous components, and small and thin form factor. However, to make such an interposer-based 3D IC feasible and reliable, numerous challenging issues on design, testing, and diagnosis remain to be resolved.
This thesis addresses the testing and characterization of interposer wires in a 2.5-D stacked IC, which is essential for yield learning and silicon debug. The proposed method provides a number of distinctive features beyond previous works on interposer wire testing. First of all, we target not only catastrophic types of faults (such as stuck-at faults or hard bridging faults) but also parametric types of faults (including both resistive open faults and resistive bridging faults between interposer wires). Secondly, our method can also be used to characterize the propagation delay across each fault-free interposer wire.

Abstract i
摘要 ii
誌謝 iii
Content iv
List of Figures vi
List of Tables viii
Chapter 1 Introduction 1
1.1 Introduction 1
1.2 Thesis Organization 4
Chapter 2 Preliminaries 5
2.1 Electrical Model of an Interposer Wire 5
2.2 VOT-Based Oscillation-Test for TSVs 7
Chapter 3 Proposed DfT Circuit 10
3.1 Design-for-Testability Circuit 10
3.2 Test Strategies 14
Chapter 4 Post-Bond Test Method 17
4.1 Testing and Characterization Flow 17
4.2 Fault Detection 19
4.3 Post-Silicon Quantification of Variation 20
4.4 Fault Type Classification 22
4.5 Delay Prediction 26
4.6 Miscellaneous Issues 29
4.7 Test Integration 31
Chapter 5 Experimental Results 34
5.1 Resistive Open Fault Detection Capability 34
5.2 Resistive Bridging-Fault Detection Capability 36
5.3 Accuracy of IW-Delay Prediction 38
5.4 Test Time Estimation 40
5.5 Area Overhead Estimation 41
Chapter 6 Conclusion 43
Bibliography 44

[1] Bassi, A. Veggetti, L. Croce, and A. Bogliolo, “Measuring the Effects of Process Variations on Circuit Performance by Means of Digitally Controllable Ring Oscillators,” Proc. of Microelectronic Test Structures, pp. 214-217, March 2003.
[2] C.-C. Chi, E. J. Marinissen, S. K. Goel, and Cheng-Wen Wu, “Post-Bond Testing of 2.5D-SICs and 3D-SICs Containing a Passive Silicon Interposer Base,” Proc. of Int’l Test Conf., pp. 1-10, Sept. 2011.
[3] C.-C. Chi, E. J. Marinissen, S. K. Goel, and C.-W. Wu, “Multi-Visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base,” Proc. of Asian Test Symp., pp. 451-456, 2011.
[4] P. Das, B Amrutur, H. S. Jamadagni, N.V. Arvind, and V. Visvanathan, "Within-Die Gate Delay Variability Measurement Using Re-Configurable Ring Oscillator," Proc. of IEEE Custom Integrated Circuits Conference(CICC), pp.133-136, Sept. 2008.
[5] L. S. Dutta and T. Hillmann-Ruge, “Application of Ring Oscillators to Characterize Transmission lines in VLSI Circuits,” IEEE Trans. on Components, Packaging, Manufacturing Technology, vol. 18, no. 4, pp. 651–657, Nov. 1995.
[6] K. S.-M. Li, C. L. Lee, C. Su, and J. E. Chen, “Oscillation Ring Based Interconnect Test Scheme for SoC,” Proc. of IEEE Asia South Pacific Design Automation Conf. (ASP-DAC), pp. 184–187, 2005.
[7] K. S.-M. Li, C.-L. Lee, C.-C. Su, Y.-M. Chang, and J.-E. Chen, “IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection,” Journal of Electronic Testing: Theory and Applications, Vol. 23, No. 4, pp. 341-355, Aug. 2007.
[8] Y.-H. Lin, S.-Y. Huang, K.-H. Tsai, W.-T. Cheng, S. Sunter, Y.-F. Chou, and D.-M. Kwai, “Small Delay Testing for TSVs in 3D ICs,” Proc. of IEEE Design Automation Conf., June 2012.
[9] Y.-H. Lin, S.-Y. Huang, K.-H. Tsai, W.-T. Cheng, S. Sunter, Y.-F. Chou, and D.-M. Kwai, "Parametric Delay Test of Post-Bond TSVs in 3-D ICs via VOT Analysis", IEEE Trans. on Computer-Aided Design of Electronic Circuits (TCAD), Vol. 32, No. 5, pp.-737-747, May 2013.
[10] E. J. Marinissen, C.-C. Chi, J. Verbree, and M. Konijnenburg, “3D DfT Architecture for Pre-Bond and Post-Bond Testing,” Proc. of IEEE 3D Systems Integration Conf., pp. 1-8, 2010.
[11] Nadeau-Dostie, J. F. Cote, H. Hulvershorn, and S. Pateras, “An Embedded Technique for At-Speed Interconnect Testing”, Proc. of IEEE Int’l Test Conf., pp. 431-438, 1999.
[12] P. R. O’Brien and T. L. Savarino, “Modeling the Driving-Point Characteristic of Resistive Interconnect for Accurate Delay Estimation,” Proc. of IEEE Design Automation Conf., pp. 512–515, Nov. 1989.
[13] R. Pendurkar, A. Chatterjee, Y. Zorian, "Switching Activity Generation with Automated BIST Synthesis for Performance Testing of Interconnects", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, No. 9. pp. 1143-1158, Sept. 2001.
[14] S. H. Wu, D. Drmanac, L.-C. Wang, “A Study of Outlier Analysis Techniques for Delay Testing,” Proc. of IEEE Int’l Test Conf., pp. 1-10., 2008.
[15] F. Ye and K. Chakrabarty, “TSV Open Defects in 3D Integrated Circuits: Characterization, Test, and Optimal Spare Allocation”, Proc. of IEEE Design Automation Conf., pp. 10240-1030, June 2012.
[16] IEEE Computer Society, “IEEE Std 1149.1 TM-2001, IEEE Standard Test Access Port and Boundary scan Architecture”, IEEE, June, 2001.
[17] “CIC Reference Flow for Cell-based IC Design”, Chip Implementation Center, CIC, Taiwan, Document no. CIC-DSD-RD-08-01, 2008.