因為高速傳輸的需求日漸成長，多輸入多輸出的技術更加受歡迎，因此，設計一個高效能且低複雜度的多輸入多輸出的偵測器是一個重要議題。晶格縮減可以藉由強化傳輸矩陣來提升偵測的效能，另一方面循環式的偵測及解調可藉著交換可信度訊息來提升傳輸效果。這篇論文著重於結合這兩者的技術並且設計一種有效計算可信度訊息的方法。儘管運用晶格縮減的偵測器無法在偵測中加入可信度訊息，但是我們的演算法在高傳輸的多輸入多輸出系統中效能上超越許多循環式的偵測及解調演算法和運用晶格縮減的軟式輸出偵測器。最後我們提出來的演算法在TSMC 90nm 1P9M CMOS的製程下能達到6.4G LLRs/s的超快傳輸速度。

Because the demand of high-throughput transmission grows in recent years, the multiple-input multiple-output (MIMO) has become a popular technique to increase the trans-mission throughput. Thus, design of a high-performance and low-complexity MIMO detector is an important issue. To improve the performance of a MIMO detector, lattice-reduction (LR) has been proposed to enhance the property of the channel matrix. On the other hand, iterative detector-and-decoder (IDD) becomes an effective technique to improve transmission performance by exchanging reliable information such as log
likelihood ratio between a detector and a decoder. This thesis focuses on combining the LR and IDD technique and devising an effective method to calculate the reliable
information. Although the proposed LRA detector does not adopt the reliable information produced by soft-input soft-output decoder in detection process, the performance of proposed LRA soft-output K-best detector has a better performance than those of the latest IDD algorithms and existing LRA soft-output detectors in high dimension MIMO systems. Finally, the proposed LRA soft-output K-best detector is implemented in TSMC 90nm 1P9M CMOS process and occupied 3.0674mm2 core area at its maximum frequency 133.3 MHz and maximum throughput 6.4G LLRs per second when 64QAM is applied.

1 Introduction 1
1.1 MIMO Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Lattice Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 LLR Clipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 LRA soft-input soft-output detector . . . . . . . . . . . . . . . . . . . . . 4
1.5 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.6 Organization of thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Channel Model and Lattice Reduction-Aided MIMO detector 9
2.1 Channel Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 QR decomposition Algorithm with Givens Rotation Method . . . . . . . 11
2.3 Lattice Reduction Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4 Lattice-Reduction-Aided MIMO Detector . . . . . . . . . . . . . . . . . . 18
2.5 Sorting-Reduced K-best Detector . . . . . . . . . . . . . . . . . . . . . . 20
2.6 Soft-Output MIMO Detection Algorithm . . . . . . . . . . . . . . . . . . 24
2.6.1 Repeat Tree Search . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.6.2 Single Tree Search . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3 Proposed Soft-Output LRA MIMO Detector 31
3.1 Algorithm with optimum Fixed LLR Clipping . . . . . . . . . . . . . . . 31
ii CONTENTS
3.2 Algorithm with optimum Last LLR Clipping . . . . . . . . . . . . . . . . 37
3.3 Algorithm with optimum Last LLR Clipping and LLR reset . . . . . . . 43
3.4 ECTLLL Soft-Output SR IMP K-best Detector . . . . . . . . . . . . . . 47
4 Architecture 51
4.1 LLR calculator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.1.2 Hardware architecture . . . . . . . . . . . . . . . . . . . . . . . . 52
4.1.3 Timing schedule . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.1.4 Multiple Instances for pipeline application . . . . . . . . . . . . . 56
4.2 Fixed-point simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.3 Proposed ECTLLL Soft-Output SR K-best Detector . . . . . . . . . . . . 60
4.3.1 FPGA implementation . . . . . . . . . . . . . . . . . . . . . . . . 60
4.3.2 Core Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5 Conclusion and Future Work 65

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