在這個大容量資料存取應用日趨廣泛的現今，反及快閃記憶體在半導體記憶體中的角色重要性日益重要。由於其擁有半導體記憶體中密度最高的元件面積最小的特性，反及快閃記憶體可以用最低的成本達到相當高的細胞密度，因此降低了製造成本，且相較於傳統硬碟，其擁有低耗能與高資料吞吐量的優點。
雖然反及快閃記憶體有各種優點，但是製成的微縮已經到達二十奈米，要在平面式反及快閃記憶體上增加元件密度變的日益困難，且成本也相對地增加。為了降低成本且讓元件密度有再進一步增加的可能，各種三維堆疊的方式被提出，目前被視為下一世代大容量資料存取應用的解決方案。
現階段三維反及快閃記憶體的製程尚未成熟，在晶片的製造與光罩蝕刻的過程中仍有許多困難需要克服，因此在元件細胞陣列中會有許多因製程產生的缺陷存在，三維電路之間的干擾也相當明顯，造成電路操作上錯誤率的提高。為了改善因為這些原因所造成寫入與寫入驗證上的錯誤與效率上的降低，高容忍位元數的錯誤更正碼被應用，不過也因此造成了傳統應用在寫入驗證的二位元搜尋式錯誤位元偵測器效率大幅降低。
於是我們於零點四微米的製程下設計了一個波傳遞式錯誤位元偵測器，可大幅降低寫入驗證端的錯誤位元偵測周期數，在六萬四千位元的頁面大小下可達到十三倍的周期改善。

Today, the application of the large data storage equipment has been widely used which lead to the increased importance of the NAND flash memory. With the smallest cell area in the planar semiconductor memory, NAND Flash memory can achieve high cell density and low cost.
Even though the NAND flash memory has a lot of benefits, the process shrinking has reduced to 20nm. It has become more difficult to increase the array density and the increasing of the cost is also unacceptable. To make the both applicable, many kinds of 3D NAND flash memory structure are proposed.
But the technology of the 3D NAND flash is not good enough that there are still many issues to conquer during the chip manufacturing and etching. It will cause many defect in the cell array. To improve to error and the efficient reduction due to these reason, the large ECC tolerance bit is applied. But this method also cause the program verification efficiency reduction due to the conventional Binary Search Fail Bit Detector.
To solve this problem, we propose the Wave Propagation Fail Bit Detector apply in 0.4um which can improve the program verification fail bit detecting operation cycle significantly. It cans reduce the operation cycles in 13 times to the conventional Binary Search Fail Bit Detector scheme in the 64k bit page size.

Contents
ABSTRACT (CHINESE) IV
ABSTRACT (ENGLISH) V
ACKNOWLEDGEMENTS (CHINESE) VI
LIST OF FIGURES X
LIST OF TABLES XIII
CHAPTER 1. INTRODUCTION 1
1.1 NAND FLASH MEMORY APPLICATION 1
1.2 CHALLENGE OF NAND FLASH MEMORY 4
1.3 OVERVIEW OF THE THESIS 7
CHAPTER 2. 3-DIMENSION VERTICAL GATE (3DVG) BE-SONOS TFT NAND FLASH MEMORY 8
2.1 BANDGAP ENGINEERED SONOS (BE-SONOS) MEMORY DEVICE 8
2.2 ARRAY ORGANIZATION 11
2.3 READ OPERATION 13
2.4 PROGRAM OPERATION 14
2.4.1 Program 14
2.4.2 Self-Boost Program Inhibit (SBPI) Technique 15
2.4.3 Program Verification Algorithm 17
2.4.4 Incremental Step Pulse Programming (ISPP) 19
2.5 ERASE OPERATION 20
2.5.1 Hole Tunneling Erase 20
2.5.2 Self-Boost Erase Inhibit Technique (SBEI) 21
2.5.3 Erase Verify Algorithm 22
CHAPTER 3. FAIL BIT DETECTION IN PROGRAM VERIFICATION 25
3.1 PAGE BUFFER STRUCTURE 25
3.2 FAIL BIT DETECTING STRUCTURE 28
3.3 THE CHALLENGE OF FBD IN 3D STRUCTURE AND 32
3.3.1 BL Coupling Noise 33
3.3.2 Source Line Noise 38
3.3.3 Layer by layer VTH requirement 39
3.3.4 Background Pattern Dependency (BPD) 40
3.4 THE ERROR CORRECTING CODE APPLICATION IN NAND FLASH 42
CHAPTER 4. CONVENTIONAL FAIL BIT DETECTOR 44
4.1 CURRENT TYPE FAIL BIT DETECTOR 44
4.2 BINARY SEARCH FAIL BIT DETECTOR 45
CHAPTER 5. PROPOSED FAIL BIT DETECTOR 50
5.1 THE IDEA OF WAVE-PROPAGATION FAIL BIT DETECTOR 50
5.2 THE CIRCUIT OF WAVE-PROPAGATION FAIL BIT DETECTOR 53
5.3 THE OPERATION OF THE WP-FBD 57
CHAPTER 6. ANALYSIS AND COMPARISONS 60
6.1 OPERATION CYCLES COMPARISON OF CONVENTIONAL BS-FBD AND PROPOSED WP-FBD 60
6.2 THE PROPAGATION DELAY ISSUE 62
6.3 RACING CONDITION ANALYSIS 65
6.4 THE OVERALL COMPARISON BETWEEN CONVENTIONAL AND PROPOSED SCHEME 67
CHAPTER 7. CHIP IMPLEMENTATION 68
7.1 TEST CHIP STRUCTURE 68
7.2 SIMULATION RESULT AND LAYOUT 69
CHAPTER 8. EXPERIMENTS AND CONCLUSION 71
8.1 EXPERIMENTS 71
8.2 CONCLUSIONS AND FUTURE WORK 73
REFERENCE 76

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