隨著科技的演進，摩爾定律勢必在近年來走到極限。而三維堆疊的出現是延續摩爾定律的一道曙光。目前三維製程的開發是各研究機關及業界最熱門的話題，三維堆疊有助於系統整合，可以減小電路尺寸以及在電路板上的傳輸損失。目前仍有許多問題需要被解決，如:直通矽穿孔之大負載導致效能不彰、直通矽穿孔過大使得面積效益不佳，以及為了提升傳輸效率而增加頻寬之效能問題等等。因此如何提高TSV之傳輸效率以及設計適合堆疊之架構已經成為了三維製程整合的重要議題。能在多層堆疊下，保有正確的傳輸機制，以及節省傳輸所消耗的能量是需要被探討的。
因此，在論文中我們提出了電荷共享傳輸方案，其中包含了電荷共享傳輸方案及半主從式堆疊架構兩種方案。其中電荷共享傳輸方案能夠節省在高附載傳輸端所消耗的能量，無須再每筆傳輸對矽晶穿孔做充電，可以克服再多數量輸出時造成功耗過大的問題，在多層堆疊的情形下更能夠有效降低傳輸功耗的損失。以及可以適應現今寬輸入輸出之規格。半主從式堆疊結構相較於主從式以及直接堆疊下有許多優點，半主從式結構有著良好的堆疊特性以及擁有可以再打線前完成測試，大幅的增加良率等許多好處。主要的時脈從主層驅動，而由各自的僕層產生自己的時脈，可以因應每層不同的製程變異，增加整體的良率。
我們使用九十奈米互補金氧半技術來驗證我們的想法，完成了一個由六萬四千字元所組成的三維靜態隨機存取記憶體，模擬結果顯示在存取時間上增快了82%，而量測結果顯示在堆疊十六層時較單端輸出有32%的功耗降低。

With the evolution of technology, Moore's Law will go to the limit in recent years. Three-dimensional stack is a good method of the continuation of Moore's Law. The development of three-dimensional process is the most popular topic of research institutions and industry, three-dimensional stack integration can reduce the circuit size and the transmission loss in the circuit board. There are still many problems to be solved and 3D integration is the hottest topic to solve these problems and provide outstanding performance and high density at the same time. But there are many issues surfaced such as the heavy loading of TSV, large TSV pitch and power issue in Wide I/O. Therefore, how to improve the transfer performance and provide efficiency circuit architectures has been an important issue.
In the thesis, we proposed the Charge-Sharing Transfer Scheme to reduce the power consumption of TSV and our circuit does not need pre-charge in every cycle time. We use small swing sensing for reducing large capacitor loading effect. Our circuit can overcome the large power consumption in wide I/O issue. And we proposed the Semi-Master Slave scheme to solve the stacking conditions such like yield, at-speed testing, and die-to-die variation. By our tracking scheme, we can stack our IC in multi-numbers of stacking.
A 64kb 2 layer 3D-SRAM macro has been fabricated in 90nm bulk CMOS technology to verify the idea of this work. Our circuit has 82% access time improved and 32% power reduction, compare to single end transfer scheme.

Contents
摘要 i
Abstract ii
致謝 iii
Contents iv
List of Figures vii
List of Tables x
Acronyms xi
Chapter1 Introduction 1
1.1 Motivation and Application for 3D-SRAM 1
1.2 Emerging Technology: 3D-IC 4
1.2.1 Die/Wafer Assembly 4
1.2.2 Bonding Styles 5
1.3 Thesis Organization 6
Chapter2 Characteristic and Analysis of ITRI 3D IC Process 7
2.1 Introduction to ITRI 3D IC Process 7
2.2 Introduction to different TSV Process 9
2.3 RC Characteristic Analysis for ITRI 3D Process 10
Chapter3 Architecture of 3D SRAM 13
3.1 Novel Architecture for 3D Memory Integrated Application 13
3.1.1 Conventional Direct Stacking and Master-Slave Architecture 14
3.1.2 Semi Master-Slave Architecture 16
3.1.3 3D Multi-Ported SRAM Arrays 17
3.1.4 3D Ultra-high Bandwidth Memory 20
3.1.5 3D System Integration Using Inductive-Coupling Link 22
3.2 Wide I/O Standard Design 25
3.2.1 Wide I/O standard 25
3.2.2 Wide I/O in 3D DRAM 25
Chapter4 Proposed Charge-Sharing Transfer Scheme 27
4.1 Concepts of Proposed Charge Sharing Scheme 27
4.2 Charge-Sharing Transfer Scheme 29
4.3 Self-Timed Tracking Scheme 33
4.4 Clamping circuit 37
Chapter5 Analyses and Comparisons of Charge-sharing Scheme 42
5.1 Speed Comparison of Charge-Sharing, Single End& STDT 42
5.1.1 Transfer Speed Using the Same Driver Size 42
5.2 Power Consumption of Charge sharing scheme 44
5.2.1 Power Consumptions compare to STDT scheme 45
5.2.2 Power Consumptions compare to Traditional Single-ended scheme 48
Chapter6 Macro Implementation 50
6.1 Architecture of Proposed 3D-SRAM 50
6.2 Test Chip Design 55
Chapter7 Experimental Results and Conclusions 57
7.1 Measurement Results 57
7.2 Conclusion of This Thesis 62
7.3 Future work 65
References 66

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