近年可攜帶之智慧型電子產品之流行與普及為系統設計帶來新的問題。在有限的電池能量供應之下必須同時達到省電以及維持系統之高效率操作。傳統方法所使用之雙巨集（2-MACRO）架構雖可以低成本達到系統的工作需求，但面臨有限的電池供應，雙巨集架構在系統待機的時候必須花費大量能量與時間保存資料。而促使單巨集（1-MACRO）架構之出現。
利用新式非揮發性記憶體的低功耗，快速，可與邏輯製程相容之特性，本篇論文提出了一種新式的5T2R三元內容循址記憶體細胞設計。使用電阻式記憶體元件代替靜態隨機存取記憶體細胞（SRAM）作為儲存元件，大大減少三元內容循址記憶體細胞之面積，同時擁有待機狀態零漏電電流（leakage current）的特色，更加降低功耗。所提出之5T2R三元內容循址記憶體細胞利用細胞內小電流讀取電阻式記憶體之資料，以決定相符線（match-line）之放電與否。與國際上已發表之作品比較，搜尋速度以及可適應之電阻式記憶體元件之電阻值範圍都各有改善。
此篇論文展示了新式的5T2R三元內容循址記憶體細胞設計。在正常工作電壓時可達到1.6ns之access time。在大範圍的電阻值比之下皆能適應並正常進行搜尋操作，並不因此拖慢搜尋速度。而其L型細胞佈局圖可完成高密度之三元內容循址記憶體細胞陣列。

Recently, mobile and intelligent electronic devices have spread everywhere, but this has brought new issues to system design. We have to achieve low power and high system performance in a battery-limited condition. The conventional 2-MACRO architecture can reach the performance demand with a low cost; but for systems with limited battery-power, the 2-MACRO architecture may consume large power and time to store the data. The single-MACRO architecture has been developed to solve this issue.
Emerging non-volatile memory devices have low-power, high speed and are compatible with logic processes. Due to these merits, we have proposed a new 5T2R non-volatile ternary content addressable memory cell (5T2R nvTCAM cell) using this device. Replacing SRAM cell with a ReRAM device has greatly decreased the layout area of TCAM cell. Since there is zero leakage current in stand-by mode, the power consumption is further decreased. The proposed 5T2R nvTCAM cell reads the data stored in the ReRAM with a small current, and then decides whether the match-line needs to be discharged according to the compared result. Compared with previous works, the proposed 5T2R nvTCAM cell has improved the search speed and tolerable resistance ratio.
In summary, we have proposed a 5T2R nvTCAM cell design. Its access time is 1.6ns with a supply of 1V VDD. It can successfully perform search operation under a wide range of resistance ratios, and maintain a fair
8
search speed under different conditions. The special L-shaped cell layout can accomplish a high density nvTCAM cell array

摘要 6
Abstract 7
圖片清單 8
表格清單 10
Chapter 1. 簡介 11
1.1 近代之低功耗系統需求 11
1.2 低功耗應用之新興非揮發性記憶體 12
1.3 三元內容循址記憶體以及其應用 13
Chapter 2. 設計目標 15
2.1 降低搜尋能量消耗 15
2.1.1 相符線能量消耗 15
2.1.2 細胞內能量消耗 16
2.2 快速搜尋操作 16
2.3 消除待機漏電電流 16
2.4 國際已發表之作品 17
Chapter 3. 所提出之5T2R非揮發性三元內容循址記憶體細胞 23
3.1 電阻式隨機存取記憶體 23
3.1.1電阻式隨機存取記憶體之結構 23
3.1.2 轉態機制 24
3.1.3 2T1R之寫入架構的設計挑戰 25
3.1.4 電阻式隨機存取記憶體之讀取擾動 25
3.2 所提出之5T2R非揮發性三元內容循址記憶體細胞架構 26
3.3 所提出之5T2R非揮發性三元內容循址記憶體細胞寫入操作 26
3.4 所提出之5T2R非揮發性三元內容循址記憶體細胞搜尋操作 28
3.4.1電晶體MML之尺寸 30
Chapter 4. 分析與比較 31
4.1 5T2R細胞之電晶體Mrd之尺寸分析 31
4.2 搜尋操作之相符線放電時間分析 32
4.3 搜尋功耗分析 37
4.4 比較表格 39
Chapter 5. 晶片實作 40
5.1 細胞佈局圖 40
5.1.1 L型細胞佈局圖 40
5.1.2 細胞面積比較 40
5.2 巨集完整電路架構 42
5.3 晶片資料總結表格 43
5.4 晶片空照圖 43
Chapter 6. 實驗結果與結論 44
6.1 測試晶片之量測方式 44
6.2 搜尋量測波形圖 45
6.3 結論 48
Chapter 7. 參考文獻 49

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