在軍用頻段中，35 GHz是常使用的頻率，常用於飛彈與雷達系統。此外，在無線通訊領域中，使用天線陣列所得到的訊雜比，會比起僅用單一天線要來得好，主要是因為天線陣列中每根天線在接收或發射的訊號可以有相位差異，藉由這些資訊交由後端數位訊號處理，能夠達到提升訊雜比的目的。

　　本論文提出一個操作在35 GHz具可調變相位功能之鎖相迴路，在壓控振盪器的部份，加入了自我注入的機制，以降低振盪器本身的相位雜訊，因為操作頻率相當高，因此第一級除頻器使用了注入鎖定式除頻器，接著在降頻後，將一組正交訊號輸入兩個可調增益放大器(PGA)中，藉由調整增益，並利用三角函數之和角公式的概念，達到輸出訊號可調整相位之功能。另外在輸入端部份，參考訊號可由訊號產生器或另一顆具三角積分調變功能之鎖相迴路提供，若由後者提供，可再增加相位雜訊之表現。

　　本文共分五章，第一章主要介紹研究動機及背景；第二章主要在分析鎖相迴路之架構、內部各子電路的操作原理以及對於雜訊議題的討論；第三章對於本論文所提出的具可調變相位功能三百五十億赫茲鎖相迴路作介紹，包括選用架構及所應用之原理推導；第四章則是呈現軟體的模擬的結果，並做討論；最後第五章作總結，對整篇論文做一個結論，並歸納出未來展望。

In the military band, frequency of 35 GHz is commonly used in missile and radar systems. Additionally, In wireless communications, the use of an antenna array have a better SNR than a single antenna since each of the antennas in an antenna array at the receiver or transmitter can have a phase difference between the signals. We can achieve the purpose to enhance the SNR by referring the information to the back-end digital signal processing.

This thesis presents a phase-locked loop with phase rotated function operating at 35 GHz . We joined a sub-injection architecture in VCO to reduce the phase noise of the oscillator itself. The first stage divider is using injection locking frequency divider. After underclocking, we give a set of orthogonal signal into two programmable gain amplifier(PGA). It can adjust the phase of the output signal by adjusting the gain of PGA and using some trigonometric function. Furthermore, the reference signal can be generated by pulse generator or another PLL which is equipped with delta-sigma modulation function. The latter can further increase phase noise performance.

This paper is organized into five chapters, the first chapter introduces the research motivation and background; second chapter is the analysis of phase-locked loop structure , the internal operation of each sub-circuit principle ,and some noise issues for discussion; the third chapter for this thesis presented with phase-locked loop with phase rotated function operating at 35 GHz be introduced, including the selection of the structure and the derivation of the application principle ;fourth chapter is to present the results of the simulation , and do some discuss; final chapter as a summary of the entire thesis to make a conclusion, and summarize the future outlook.

第一章 緒論
　1.1簡介
　1.2章節介紹

第二章 鎖相迴路原理及設計
　2.1鎖相迴路架構分析及操作原理
　　2.1.1相位頻率檢測器
　　2.1.2電流幫浦
　　2.1.3迴路濾波器
　　2.1.4壓控振盪器
　　2.1.5除頻器
　2.2鎖相迴路轉移函數分析
　2.3鎖相迴路之雜訊分析

第三章 一個使用TSMC 65nm製程的35GHz具可調變
　　　 相位功能鎖相迴路之設計與實現
　3.1鎖相迴路設計流程
　3.2鎖相迴路基本參數
　3.3相位頻率檢測器設計介紹
　3.4電流幫浦設計介紹
　3.5迴路濾波器設計介紹
　3.6壓控振盪器設計介紹
　3.7除頻器設計介紹
　　3.7.1注入鎖定式除頻器
　　3.7.2電流模式邏輯式除頻器
　　3.7.3真單相時脈式除頻器
　3.8可調增益放大器及相位調整原理之介紹

第四章 模擬結果及數據
　4.1相位頻率檢測器
　4.2電流幫浦
　4.3壓控振盪器
　　4.3.1共振腔阻抗
　　4.3.2壓控振盪器輸出頻率範圍
　　4.3.3相位雜訊
　　4.3.4輸出波形與頻率
　4.4除頻器
　4.5迴路鎖定情形
　4.6電路佈局

第五章 結論與未來展望
　5.1結論
　5.2未來展望

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