帳號:guest(18.226.170.41)          離開系統
字體大小: 字級放大   字級縮小   預設字形  

詳目顯示

以作者查詢圖書館館藏以作者查詢臺灣博碩士論文系統以作者查詢全國書目
作者(中文):王宗曄
作者(外文):Wang, Zong Ye
論文名稱(中文):可記錄多通道神經訊號之低雜訊低功耗 放大器設計
論文名稱(外文):Design of a low-noise, low-power amplifier for multichannel neural recording
指導教授(中文):陳新
指導教授(外文):Chen, Hsin
口試委員(中文):謝秉璇
彭盛裕
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學號:100061466
出版年(民國):103
畢業學年度:102
語文別:中文
論文頁數:105
中文關鍵詞:低雜訊放大器神經訊號
外文關鍵詞:Low noise amplifierNeural signal
相關次數:
  • 推薦推薦:0
  • 點閱點閱:638
  • 評分評分:*****
  • 下載下載:14
  • 收藏收藏:0
近年來,隨著CMOS技術的發展與製程工藝的不斷提高,產生了許多積體電路在生物醫學中的應用,利用植入式腦機介面裝置治療帕金森氏症、癲癇等疾病越來越廣泛的受到關注與研究。
本論文旨在研究用於深腦電刺激療法治療帕金森氏症的植入式腦機介面晶片系統中最前端的生醫放大器。由於連續的電刺激不僅僅會抑制不正常的神經細胞活動,同時有可能抑制到患者正常的生理活動,因此我們需要設計實現一個可以在時間和空間上準確記錄到患者腦部神經訊號的前端低雜訊放大器。本論文採用截切架構令放大器達到低雜訊目的,同時應用八組放大器來實現多通道記錄的效果。本論文共設計與量測了三個版本的放大器,由於第一版截切放大器八組外部電容佔用很大面積,第二版放大器採用共用輸入端電容的方法來實現多通道記錄,希望達到減少電容面積的目的,並通過模擬與電性量測探討了這一方法的可行性。同時在這一版我們加入了抑制刺激干擾的功能。在與生科系合作中,我們以第二版放大器為平台進行了動物實驗,成功用多通道方式記錄到帕金森氏症老鼠的異常腦波。在第二版本放大器的量測中我們發現一些不足,例如在多通道記錄時扭轉速率不夠、線性度不理想以及偏壓電流源易受電源供應雜訊影響,本論文設計了第三版本用於腦機介面系統中的前端低雜訊放大器。依據三個版本的設計與量測,本論文總結了一些生醫放大器的設計考量與經驗。
In recent years, with the development of CMOS technology and the improvement of process, a number of integrated circuits have been used in biomedical applications. For instance, implantable brain-machine interfaces for treating Parkinson’s disease, epilepsy, and other diseases have attracted more and more attentions and research resources.
This thesis aims to study the frontend biomedical amplifier used in the brain-machine interface for studying the mechanism of deep brain stimulation (DBS) and the therapy for the Parkinson’s disease. The continuous, periodic DBS not only inhibits abnormal neuron activities but also suppresses some normal physiological activities. Therefore, a low-noise, frontend amplifier able to record multi-channel local field potentials (LFPs) is demanded. The LFP recordings are not only crucial for positioning the stimulation electrodes optimally but also for controlling stimulation in a closed-loop manner. This thesis uses a chopper technique to achieve the low-noise performance, and eight chopper amplifiers are employed for multi-channel recording. Three versions of amplifiers are designed and tested. While the first version required external capacitors, the second version investigates the feasibility of sharing embedded capacitors among different channels. The main purpose is to minimize the area and power consumption, and the feasibility is discussed according to both simulation and electrical measurement results. In addition, fast-settling control is added to eliminate the stimulation artifact. With the help from the life and science department, we use the second version amplifier to do biological experiment and get some data from the Parkinson’s disease rat successfully, including abnormal neuron potentials. However, the second version is found to exhibit some hardware non-idealities, including the slew rate, the linearity, and VDD noise resistibility. Therefore, we summarize the drawbacks and design the third version of the low-noise amplifier. According to the testing of the three versions of amplifiers, the design guidelines and considerations will be concluded in the thesis.
致謝 I
摘要 III
Abstract V
目錄 VII
圖目錄 IX
表目錄 XV
第一章 緒論 1
1.1 背景介紹 1
1.2 腦機介面系統簡介 1
1.3 研究動機 2
1.4 章節簡介 3
第二章 文獻回顧 5
2.1 神經訊號特性及神經-電極介面模型 5
2.2 傳統低雜訊生醫放大器 7
2.3 採用截切(chopping)技術的低雜訊生醫放大器 10
2.4 截切放大器雜訊分析 16
2.5 第一版截切放大器設計概念 18
2.6 討論總結 21
第三章 第一版截切放大器量測與分析討論 23
3.1 晶片電性量測平台 23
3.2 放大倍率之量測結果 25
3.3 頻率響應之量測結果 26
3.4 雜訊之量測結果 28
3.5 DSL與RRL之量測結果 31
3.6 量測結果之分析與總結 32
第四章 第二版截切放大器設計、量測與分析 35
4.1 相較於第一版主要之改進 35
4.1.1輸入電容、截切頻率選擇之分析 35
4.1.2 Fast settling與ripple reduction功能之分析 37
4.1.3共用電容探討設計 40
4.2 前端放大器多通道操作模式及模擬 42
4.3 電性量測平台與結果 46
4.3.1 電性量測平台 46
4.3.2 暫態響應、頻率響應與雜訊量測結果 48
4.3.3 Ripple reduction與Fast settle量測結果 51
4.3.4 兩種多通道模式量測結果 58
4.4 生物量測平台與結果 64
4.5 量測結果之分析與總結 72
第五章 第三版截切放大器設計與實現 75
5.1 相較於第二版主要之改進 75
5.1.1線性度之分析與改進 75
5.1.2扭轉速率(slew rate)之分析與改進 79
5.1.3自立式參考電流源(bootstrap current source)之設計 81
5.2 第二級放大器設計與模擬結果 84
5.3 應用於腦機介面系統中前端放大器的模擬與晶片實現 86
5.4 電性量測平台與結果 96
第六章 結論與未來研究方向 100
6.1 結論 100
6.2 未來研究方向 101
參考文獻 102

[1] H. Berger, “On the Electroencephalogram of man,” 1969:Suppl 28:37+.
[2] W. R. Patterson, M. Ieee, Y. Song, C. W. Bull, D. A. Borton, F. Laiwalla, S. Park, Y. Ming, J. Aceros, and M. Ieee, “Listening to Brain Microcircuits for Interfacing With External World V Progress in Wireless Implantable Microelectronic Neuroengineering Devices,” Proceedings of the IEEE, vol. 98, no. 3, pp. 375–388, 2010.
[3] R. R. Harrison, “A Versatile Integrated Circuit for the Acquisition of Biopotentials,” 2007 IEEE Cust. Integr. Circuits Conf., no. Cicc, pp. 115–122, 2007.
[4] Phillip E. Allen, Douglas R. Holberg, “CMOS Analog Circuit Design,” Second Edition, p403.
[5] R. R. Harrison, C. Charles, and S. Member, “A Low-Power Low-Noise CMOS Amplifier for Neural Recording Applications,” IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 958–965, 2003.
[6] C. C. Enz and G. C. Temes, “Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization,” Proc. IEEE, vol. 84, no. 11, pp. 1584–1614, 1996.
[7] I. G. Finvers, J. W. Haslett, S. Member, F. N. Trofimenkoff, and S. Member, “Noise Analysis of a Continuous-Time Auto-Zeroed Amplifier,” IEEE Transactions on Circuits and Systems, vol. 43, no. 12, 1996.
[8] D. G. Messeiuchmitt and S. Member, “A Low-Noise Chopper-Stabilized Differential Switched-Capacitor Filtering Technique,” IEEE J. Solid-State Circuits, no. December, pp. 708–715, 1981.
[9] Phillip E. Allen, Douglas R. Holberg, “CMOS Analog Circuit Design,” Second Edition, p412.
[10] Q. Fan, S. Member, F. Sebastiano, S. Member, J. H. Huijsing, L. Fellow, and K. A. A. Makinwa, “A 1 . 8 W 60 nV Hz Capacitively-Coupled Chopper Instrumentation Ampli fi er in 65 nm CMOS for Wireless Sensor Nodes,” IEEE J. Solid-State Circuits, vol. 46, no. 7, pp. 1534–1543, 2011.
[11] N. Van Helleputte, S. Kim, H. Kim, J. P. Kim, C. Van Hoof, and R. F. Yazicioglu, “A 160 μA biopotential acquisition IC with fully integrated IA and motion artifact suppression.,” IEEE Trans. Biomed. Circuits Syst., vol. 6, no. 6, pp. 552–61, Dec. 2012.
[12] N. Verma, A. Shoeb, J. Bohorquez, J. Dawson, J. Guttag, and A. P. Chandrakasan, “A Micro-Power EEG Acquisition SoC With Integrated Feature Extraction Processor for a Chronic Seizure Detection System,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 804–816, Apr. 2010.
[13] R. W. R. Wu, K. a. a. Makinwa, and J. H. Huijsing, “A Chopper Current-Feedback Instrumentation Amplifier With a 1 mHz 1/f Noise Corner and an AC-Coupled Ripple Reduction Loop,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3232–3243, 2009.
[14] Jo-Yu Wu, “A Band-Tunable, Low-Noise, Multichannel Amplifier with AP/LFP Separation for Neuronal Recording and Dual-threshold adaptive AP detector,” 2011,碩士論文
[15] Y. C. Chen, Y. T. Lee, S. R. Yeh, H. Chen, “A bidirectional, flexible neuro-electronic interface employing localised stimulation to reduce artifacts,” 2009 4th Int. IEEE/EMBS Conf. Neural Eng., pp. 46–50, Apr. 2009.
[16] D.L. Robinson, M.E. Goldberg, G.B. Stanton, “Parietal Association Cortex in the Primate: Sensory Mechanisms and Behavioral Modulations,” J. Neurophysiology, vol. 41, no. 4, pp.910-32, July 1978
[17] C. Deransart, B. Hellwig, M. Heupel-Reuter, J.-F. Léger, D. Heck, and C. H. Lücking, “Single-unit analysis of substantia nigra pars reticulata neurons in freely behaving rats with genetic absence epilepsy,” Epilepsia, vol. 44, no. 12, pp. 1513–20, Dec. 2003.
[18] G. Giustolisi, G. Palumbo, M. Criscione, F. Cutri, “A Low-Voltage Low-Power Voltage Reference Based on Subthreshold MOSFETs,” IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 151–154, 2003.
[19] Phillip E. Allen, Douglas R. Holberg, “CMOS Analog Circuit Design,” Second Edition, p149.
[20] R. S. Assaad, S. Member, J. Silva-martinez, and S. Member, “The Recycling Folded Cascode : A General Enhancement of the Folded Cascode Amplifier,” IEEE J. Solid-State Circuits, vol. 44, no. 9, pp. 2535–2542, 2009.
 
 
 
 
第一頁 上一頁 下一頁 最後一頁 top
* *