|
[1] C. P. Yeh(1996), “Parametric Finite Element Analysis of Flip Chip Reliability,” The International Journal of Microcircuits and Electronic Packaging, vol. 19, pp. 120-127. [2] D. C. Montgomery(2005), “Design and Analysis of Experiments,” 5th ed. John Wiley & Sons, pp. 778-780. [3] J. H. Lau(1990), “Thermal Stress Analysis of Plastic Leaded Chip Carriers,” Intersociety Conference on Thermal Phenomena, pp. 57-66. [4] J. H. Okura, K. Darbha, S. Shetty, A. Dasgupta(1999), “Guidelines to Select Underfills for Flip Chip on Board Assemblies,” IEEE, Electronic Components and Technology Conference, pp. 589-594. [5] K. N. Chiang, Z. N. Liu, J. D. Lin and Y. T. Lin(2000),“A New Approach for No-Underfill Flip Chip Package Design,” Power Mechanical Engineering, National Tsing Hua University. [6] L. L. Mercado and V. Sarihan(1999),“Predictive Design of Flip-Chip PBGA for High Reliability and Low Cost,” Electronic Components and Technology Conference, pp. 342-348. [7] L. L. Mercado, H. Wieser, T. Hauck(2001), “Mold Delamination and Die Fracture Analysis of Mechatronic Packages,” IEEE Electronic Component and Technology Conference. [8] M. W. Lee, J. Y. Kim, J. D. Kim and C. H. Lee(2010), “Below 45nm low-k layer stress minimization guide for high-performance flip-chip packages with copper pillar bumping,” Electronic Components and Technology Conference(ECTC), 2010 Proceedings 60th, pp. 1623-1630. [9] S. Timoshenko(1925), “Analysis of Bi-Metal Thermostats,” J. Opt. Soc. Am.,vol. 11, pp. 233-255. [10] S. Groothuis, W. Schroen, and M. Murtuza(1985), “Computer Aided Stress Modeling for Optimizing Plastic Package Reliability,” IEEE/IRPSConference, pp. 184-191. [11] T. Y. Lin, Z. P. Xiong, Y. F. Yao(2003), “Failure Analysis of Full Delamination on the Stacked die Leaded Packages,” Transactions of the ASME Journal of electronic packing, vol. 125, pp. 392-399. [12] T. Y. Pan and Y. H. Pao(1990), “Deformation in Multilayer Stacked Assemblies,” Journal of Electronic Packaging, vol. 112, pp. 30-34. [13] W. T. Chen and C. W. Nelson(1979), “Thermal Stress in Bonded Joints,” IBM Journal of Research and Development, vol. 23, pp. 179-188. [14] W. S. Lee, I. Y. Han, J. Yu, S. J. Kim, and K. Y. Byun(2006), “Thermal Characterization of Thermally Conductive Underfill for a Flip-Chip Package Using Novel Temperature Sensing Technique,” Thermochimica Acta, vol. 455, pp. 148-155. [15] Y. He(2005), “Thermal Characterization of Overmolded Underfill Materials for Stacked Chip Scale Packages,” Thermochimica Acta, vol. 433, pp. 98-104. [16] 李承傑(1995), “三維導線架型式構裝翹曲與應力分析,” 雲林科技大學機械工程研究所碩士論文. [17] 陳潔蓓(2002), “導線架型3D 堆疊構裝設計與脫層之預防研究,” 元智大學機械工程研究所碩士論文. |