由於電阻式記憶體擁有低價格、低功耗、快速的讀寫速度與製程中晶片較不易受到損毀，引起了許多科學家廣泛的研究興趣。而為了要因應規格的縮小化，利用奈米線來取代薄膜已成為一種趨勢。在許多的研究報導中，都是先在基板上合成出純鎳奈米線，再將此氧化後得到核殼狀鎳/氧化鎳的奈米線，因此，屬於二階段製程。本研究中，我們成功地利用一階利段製程合成出核殼狀鎳/氧化鎳的奈米線，並針對其結構、電性與電阻轉換性質探討分析。
我們利用氯化鎳為先驅物，在溫度為800/700的兩區爐管中液流氬氣，透過OAG機制成功的在矽基材上中成長出Ni/NiO核殼狀奈米線，並且利用氫氟酸蒸氣將外層因OAG機制所生成的二氧化矽去除。我們利用不同的反應溫度與通入不同的氣體來控制外層二氧化矽的厚度。再者，利用SEM與TEM來分析奈米線的表面形貌、晶體結構與化學成分組成。接下來，透過三軸調整器與光學顯微鏡以及電子束微影技術來製作成奈米元件。
最後，我們利用Keithley 4200電流電壓量測儀器來測量Ni/NiO核殼狀奈米線的I-V曲線和電阻轉換的行為。同時，藉由不同的的電極距離來探討電阻轉換的可能傳導路徑。首先，我們利用不同的金屬做為電極，可以觀察到其擁有不同的電阻轉換特性。第二，我們將兩組作耐久度的測試，可以發現其操作次數都可高達100次並且呈現的是穩定的狀態下。最後，由於我們的操作電流可以低到micro 安培以下，因此在電阻式記憶體的應用上有著相當的潛力。

Because RRAM has many advantages such as low cost, low power, fast programming speed (twr < 100 ns), simple structure, shrinkage of cell size and nondestructive operation, it has attracted much attention for many researchers. Besides, in order to decrease the cell area and raise the density, nanowires were used to replace the thin film materials. In the literature, they usually synthesize the Ni nanowires and then oxidize the nanowires to form Ni/NiO core-shell structures. In our research, we report the growth and structural characterization of the core-shell Ni/NiO nanowires in one step. In addition, the electrical and resistance switching properties were also investigated.
The Ni/NiO core-shell nanowires were synthesized by NiCl2 sources on Si substrates at 800 ℃ in source region (I) and 700 ℃ in substrate region (II) under Ar carrier gas in two-region furnace via oxide-assisted growth (OAG) mechanism. Due to the OAG mechanism, the SiO2 layer was formed outside of Ni/NiO core-shell nanowires. Then, we used HF vapor to etch away the SiO2. By different reaction temperature and flow gas, we can control the diameters and length of the nanowires. The crystal structure, morphology and chemical composition were analyzed by scanning electron microscope (SEM) and transmission electron microscope (TEM). Besides, due to fabrication of nanodevice, we use the optical microscope (OM) and a series of standard electron beam lithography (EBL).
Finally, we used the Keithley 4200 to measure the I-V curve and resistive switching behaviors of core-shell Ni/NiO nanowires. Also, we designed different electrode distances of nanodevices to investigate the possible conduction path. First, different resistive switching modes such as unipolar or bipolar switching mode were observed in different electrodes, nickel and titanium. Secondly, the endurance of the Ni/NiO core-shell nanowires can be modified and the cycle number can be over 100. Finally, because the resistive switching current could be operated at micro amp (A) and lower power, the Ni/NiO core-shell nanowires have potential to become energy efficient random access memory (ReRAM).

Contents I
The Index of Figures III
The Index of Tables V
Acknowledgments VI
Abstract VII
摘要 VIII
Chapter 1 1
Introduction 1
1.1 Nanotechnology 1
1.2 Nanomaterials 3
1.2.1 One-Dimensional Nanostructures 3
1.3 Growth Mechanisms of Nanowires 6
1.3.1 Vapor-Liquid-Solid Growth (VLS) Mechanism 6
1.3.2 Vapor-Solid Growth (VS) Mechanism 7
1.3.3 Solution-Liquid-Solid (SLS) Growth Mechanism 8
1.3.3 Oxide-Assisted Growth (OAG) Mechanism 9
1.4 Ni Nanowires 13
1.4.1 Synthesis of the Ni Nanowire 13
1.5 Memory 15
1.5.1 FeRAM (Ferroelectric Random Access Memory) 15
1.5.2 MRAM (Magnetoresistive Random Access Memory) 16
1.5.3 PRAM (Phase-change Random Access Memory) 16
1.5.4 RRAM (Resistance Random Access Memory) 17
1.6 Mechanisms of RRAM (ResistanceRAM) 23
1.6.1 Thermalchemical Mechanism 23
1.6.2 Electrochemical metallization Mechanism 24
1.6.3 Electrochemical metallization Mechanism 24
1.7 NiO in RRAM 32
1.8 Motivation 37
Chapter 2 38
Experimental Procedures 38
2.1 Synthesis of Core-Shell Ni/NiO Nanowires 38
2.1.1 Synthesis of the Ni Nanowires 39
2.1.2 Etching the SiO2 by HF Vapor 39
2.1.3 RTA to Form the Uniform NiO Shell 39
2.1.4 Nanodevices Fabrication 40
2.1.4.1 Chip Cleaning 41
2.1.4.2 Sample Preparation and Pick up Nanowires 41
2.1.4.3 Locate Nanowires and Design Pattern 41
2.1.4.4 Photoresist Spin Coating and Soft Baking 41
2.1.4.5 EBL (Electron Beam Lithograply) 42
2.1.4.6 Development 42
2.1.4.7 Thermal Evaporation 42
2.1.4.8 Lift-Off Process 43
2.1.5 Electro-Characterization and RRAM Measurement 43
2.2 Property Analysis 44
2.2.1 SEM (Scanning Electron Microscope) 44
2.2.2 TEM (Transmission Electron Microscope) 44
Chapter 3 45
Result and Discussions 45
3-1 Optimization the Growth of Ni/NiO Core-Shell Nanowires 45
3-1-1 Reaction Temperature Parameter 45
3-1-2 Flow Gas Parameter 47
3-2 Properties Analysis 49
3-2-1 Surface Morphology Analysis 49
3-2-2 Structure and Composition Analysis 50
3-2-3 Mechanism of Growth Ni/NiO Core-Shell Nanowires 53
3-2-4 Electricity Analysis 55
3-3 Resistive Switching Characteristics of Ni/NiO Core-Shell Nanowires 57
3-3-1 Conducting Path in Ni/NiO Core-Shell Nanowires 61
3-3-2 Mechanism of Resistive Switching Behaviors of Ni/NiO Core-Shell Nanowires 62
Chapter 4 64
Summary and Conclusions 64
References 65

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