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作者(中文):王裕隆
作者(外文):Wang, Yu-Long
論文名稱(中文):以微波退火及非對稱性結構增強鰭式穿隧電晶體電性特性之研究
論文名稱(外文):Improving electrical characteristics of Fin-shaped Tunneling-Field-Effect-Transistor using Microwave dopant activation and Asymmetry structure
指導教授(中文):吳永俊
指導教授(外文):Wu, Yung-Chun
口試委員(中文):李敏鴻
羅廣禮
口試委員(外文):Lee, Ming-Hung
Luo, Gung-Li
學位類別:碩士
校院名稱:國立清華大學
系所名稱:工程與系統科學系
學號:100011568
出版年(民國):102
畢業學年度:101
語文別:英文中文
論文頁數:51
中文關鍵詞:穿隧電晶體微波退火非對稱性結構多晶矽鰭式電晶體
外文關鍵詞:Tunneling field effect transistorMicrowave annealingAsymmetry structurePoly-siliconFin-FET
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隨著可攜式電子產品市場需求,雖然電晶體朝著低成本高密度發展,但是元件製程和物理的限制使得要繼續維持元件特性變的更為困難。為此 ,設計出不同於一般傳統MOS電晶體的元件為一勢在必行之解決方案。
本文使用P-I-N結構之穿隧電晶體.其利用量子穿隧機制來進行操作,使元件可以經由不同於MOS電晶體飄移電流的穿隧電流來達到快速開關的特性, 使元件在OFF的狀態下漏電電流可以減少,達成低功率消耗的目的。 由於使用鰭式閘極的原因,能夠從多個方向影響主動層的電位分布,進而增加閘極對通道的控制能力,使元件特性更好。綜合以上論述,具鰭式閘極穿隧電晶體為一高效能且具有良好開關特性之元件。
在本研究中我們專注在以低溫微波退火來取代傳統高溫快速退火以形成陡峭接面.相較於傳統高溫快速退火,低溫微波退火可降低次臨界擺幅及提升穿隧電晶體的導通電流; 但在提升導通能力的同時, 我們觀察到因為熱電子效應所引發的負微分電導現象,
同時我們也觀察到因為能帶微縮及熱場發射效應,溫度對元件特性有一個正向的相關性影響。最後,我們利用源極與汲極在幾何結構上的不同,來設計出同時具有高導通電流與低漏電的非對稱性閘極穿隧電晶體。
在本文列出此結構的各項指標,以及實驗數據皆顯示出具鰭式穿隧電晶體具有應用於實際產品的高度價值,同時擁有成為下一世代元件的潛力。

The market demand for portable electric equipment increase dramatically year by year. Although transistors develop toward low cost and high density, maintaining device characteristics becomes difficult due to the device fabrication and physics limitations of the device. Designing a device that different from conventional MOSFET is a necessary way.
This thesis based on Fin-shaped Tunneling Transistor which operated by quantum tunneling mechanism. Thus, compared with conventional MOSFET operated by drift mechanism, the Tunneling Transistor can achieve fast on/off characteristic. By the Fin-shaped structure, it can affect the active layer electric potential distribution by multi-direction, increasing the gate control ability and enhance the characteristics. Above the discussion, the Fin-shaped tunneling transistor is a device with high-efficiency and good transfer characteristic.
In this thesis, we focus on demonstrate that microwave dopant activation technique can help TFETs to form an abrupt tunneling junction. Subthreshold slope and driving current can be greatly enhanced by microwave annealing as the dopant activation method compare to traditional rapid thermal annealing. An interesting phenomenon of negative differential conductance in the output characteristic was observed, which is attributed to hot-carrier effect at the high gate overdrive operation. A positive temperature dependence of transfer characteristic is also observed, which is related to the bandgap narrowing effect and the enhancement of the thermionic field emissions of the grain boundary states. Finally, with the geometric difference between source and drain, we demonstrate a device with high on-state current and low off-state current, simultaneously.
This work shows experimental data for device’s reliability; all the data can display Fin-shaped
tunneling transistor has applied to high value actually, it would become the next-generation device.
中 文 摘 要……………...………………………………………………………………………….i
Abstract……………………………………………………………………………………...................iii
Acknowledge……………………………………………………………………………………………v
Contents vii
Table Captions ix
Chapter 4 ix
Figure Captions x
Chapter 1 x
Chapter 2 x
Chapter 3 xii
Chapter 4 xi
Chapter 5 xii
Chapter 1 1
Introduction 1
1-1MOSFET Scaling in Semiconductor Industry 1
1-2 Low Power Device 6
Chapter 2 8
Basic Mechanisms of Tunneling Field Effect Transistors 8
2-1 The history of TFET 8
2-2 Principle of operation 8
2-3 Microwave 15
2-4 Motivation 16
Chapter 3 25
Device Structure and Fabrication 21
Chapter 4 25
Results and Discussion 25
4-1 Transfer characteristics 25
4-2 Geometry characteristics 26
4-3 Output characteristics 26
4-4 Temperature characteristics…………………………………………………………………..27
Chapter 5…...………………………………………………………………………………………39
Asymmetry-Gate Tunneling Field-Effect Transistor………………………………………………39
5-1 Abstract of AG-TFET……………………………………………………………………………39
5-2 Device Structure and Simulation Model………………………………………………………….. 39 5-3 Results and Discussion…………………………………………………………………………….40
Chapter 6…………………………………………………………………………………………….46
Conclusion……………………………………………………………………………………………..46
Reference………………………………………………………………………………………………47












Reference
Chapter 1
[1-1] S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, 3 ed.: John Wiley & Sons, INC., 2006.
[1-2] Lundstrom, M. S. The MOSFET revisited: device physics and modeling at the nanoscale. Proc. IEEE Int. SOI Conf. 1–3 IEEE, 2006.
[1-3] Bhuwalka, K., Schultze, J. & Eisele, I. A simulation approach to optimize the electrical parameters of a vertical tunnel FET. IEEE Trans. Electron Devices 52, 1541–1547, 2005.
[1-4] Boucart, K. & Ionescu, A. M. Double-gate tunnel FET with high-κ gate dielectric. IEEE Trans. Electron Devices 54, 1725–1733, 2007.
[1-5] Kam, H., King-Liu, T.-J., Alon, E. & Horowitz, M. Circuit-level requirements for MOSFET-replacement devices. Tech. Digest IEEE Int. Electron Devices Meet. 1 IEEE, 2008.
[1-6] Hanson, S., Seok, M., Sylvester, D. & Blaauw, D. Nanometer device scaling in subthrehold logic and SRAM. IEEE Trans. Electron Devices 55, 175–185, 2008.
[1-7] Chang, L. et al. Practical strategies for power-efficient computing technologies. Proc. IEEE 98, 215–236, 2010.
[1-8] Lucian Shifren, director of device technology at SuVolta, “Leakage power – it’s worse than you think” EE times,2011.
[1-9] Adrian M. Ionescu & Heike Riel, “Tunnel field-effect transistors as energy-efficient electronic switches,” doi:10.1038/nature10679 2011.


Chapter 2
[2-1]. Quinn, J., Kawamoto, G. & McCombe, B. Subband spectroscopy by surface channel
tunneling. Surf. Sci. 73, 190–196, 1978.
[2-2]. Banerjee, S., Richardson W., Coleman J. & Chatterjee, A. A new three-terminal
tunnel device. IEEE Electron Device Lett. 8, 347–349, 1987.
[2-3]. Takeda, E., Matsuoka, H., Igura, Y. & Asai, S. A band to band tunneling MOS device
B2T-MOSFET. Tech. Digest IEEE Int. Electron Devices Meet. 402–405, IEEE, 1988.
[2-4]. Baba, T. Proposal for surface tunnel transistors. Jpn. J. Appl. Phys. 31, L455–L457,
1992.
[2-5]. Reddick, W. & Amaratunga, G. Silicon surface tunnel transistor. Appl. Phys. Lett. 67,
494–496, 1995.
[2-6]. Koga, J. & Toriumi, A. Negative differential conductance in three-terminal silicon
tunneling device. Appl. Phys. Lett. 69, 1435–1437, 1996.
[2-7]. Hansch, W., Fink, C., Schulze, J. & Eisele, I. “A vertical MOS-gated Esaki tunneling
transistor in silicon.” Thin Solid Films 369, 387–389, 2000.
[2-8]. Aydin, C. et al. “Lateral interband tunneling transistor in silicon-on-insulator.” Appl.Phys. Lett. 84, 1780–1782, 2004.
[2-9]. Appenzeller, J., Lin, Y.-M., Knoch J. & Avouris, P. “Band-to-band tunneling in carbon nanotube field-effect transistors.” Phys. Rev. Lett. 93, 196805, 2004.
[2-10]. Krishnamohan, T., Kim, D., Raghunathan, S. & Saraswat, K. “Double-gate strained-Ge heterostructure tunneling FET (TFET) with record high drive currents and <60 mV/dec subthreshold slope.” Tech. Digest IEEE Int. Electron Devices Meet. 947–949, IEEE, 2008.
[2-11]. Mayer, F. et al. “Impact of SOI, Si1–xGexOI and GeOI substrates on CMOS
compatible tunnel FET performance.” Tech. Digest IEEE Int. Electron Devices Meet.
163–166 ,IEEE, 2008.

[2-12]. Hu, C. et al. Prospect of tunneling green transistor for 0.1 V CMOS. IEEE Int.
Electron Devices Meet. 16.1.1–16.1.4 ,IEEE, 2010.
[2-13].Moselund, K. E. et al. “Comparison of VLS grown Si NW tunnel FETs with different
gate stacks.” Proc. Eur. Solid State Device Res. Conf. 448–451, IEEE, 2009.
[2-14] Boucart, K. & Ionescu, A. M. “Double-gate tunnel FET with high-κ gate dielectric.”
IEEE Trans. Electron Devices 54, 1725–1733,2007.
[2-15] Wang, P. F. et al. “Complementary tunneling transistor for low power application.”
Solid-State Electron. 48, 2281–2286, 2004.
[2-16] Knoch, J. & Appenzeller, J. “A novel concept for field-effect transistors – the tunneling carbon nanotube FET”. Digest Device Res. Conf. 153–156, IEEE, 2006.
[2-17] Knoch, J., Mantl, S. & Appenzeller, J. “Impact of the dimensionality on the
performance of tunneling FETs: bulk versus one-dimensional devices”. Solid-State
Electron. 51, 572–578, 2007.
[2-18]. Zhang, Q., Zhao, W. & Seabaugh, A. “Low-subthreshold-swing tunnel transistors.”
IEEE Electron Device Lett. 27, 297–300, 2006.
[2-19] Knoch, J., Mantl, S. & Appenzeller, J. “Impact of the dimensionality on the
performance of tunneling FETs: bulk versus one-dimensional devices”. Solid-State
Electron. 51, 572–57, 2007.
[2-20] Q. Zhang, J. Huang, N. Wu, G. Chen, M. Hong, L. K. Bera, an C.Zhu ,“Drive-current
enhancement in Ge n-channel MOSFET using laser annealing for source/drain
activation,” IEEE Electron Device Lett., vol. 27, no. 9, pp. 728–730, Sep. 2006.
[2-21] A. T. Fiory, H.-J. Gossmann, C. Rafferty, P. Frisella, J. Hebb, and J. Jackson,
“Ultra-shallow junctions and the effect of ramp-up rate during spike anneals in
lamp-based and hot-walled RTP systems,” in Proc. Int. Conf. Ion Implantation
Technol., Kyoto, Japan, Jun. 22–26, 1998, pp. 22–25.
[2-22] C. F. Nieh, K. C. Ku, C. H. Chen, H. Chang, L. T. Wang, L. P. Huang, Y. M. Sheu,
C. C. Wang, T. L. Lee, S. C. Chen, M. S. Liang, and J. Gong, “Millisecond anneal

and short-channel effect control in Si CMOS transistor performance,” IEEE Electron Device Lett., vol. 27, no. 12, pp. 969–971, Dec. 2006.
[2-23] W. Aderhold, I. Iliopoulos, and A. Hunter, “Virtual metrology in RTP with WISR,”
in Proc. 15th IEEE Int. Conf. Adv. Therm. Process. Semicond.— RTP, 2007, pp.
101–104.
[2-24] E. L. Pankratov, “Redistribution of dopant during microwave annealing of a
multilayer structure for production p–n junction,” J. Appl. Phys.,vol. 103, no. 6, p.
064 320, Mar. 2008.
[2-25] T. L. Alford, D. C. Thompson, J.W. Mayer, and N. D. Theodore, “Dopant
activation in ion implanted silicon by microwave annealing,” J. Appl. Phys., vol.
106, no. 11, p. 114 902, Dec. 2009.
[2-26] Y.J. Lee, F.K. Hsueh, S.C. Huang, J. M. Kowalski, J. E. Kowalski, A. T. Y.
Cheng, A. Koo, G.L. Luo, and C.-Y. Wu, “A low-temperature microwave annealing
process for boron-doped ultrathin Ge epilayer on Si substrate,” IEEE Electron Device
Lett., vol. 30, no. 2, pp. 123–125, Feb. 2009.
[2-27] Anne S. Verhulst , Bart Sorée, Daniele Leonelli, William G. Vandenberghe, and
Guido Groeseneken, “Modeling the single-gate double-gate and gate-all-around tunnel field-effect transistor” JOURNAL OF APPLIED PHYSICS 107, 024518, 2010.

Chapter4
[4-1] S. Richter, C. Sandow, A. Nichau, S. Trellenkamp, M. Schmidt, R. Luptak, K. K.
Bourdelle, Q. T. Zhao, Member, IEEE, and S. Mantl, Member, IEEE”Ω-Gated Silicon
and Strained Silicon Nanowire Array Tunneling FETs” IEEE Electron Device
Letters, VOL. 33, NO. 11, NOVEMBER 2012.
[4-2] S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, 3 ed.: John Wiley &
Sons , INC., 2006.


Chapter5
[5-1] User’s Manual for Synopsys SDevice.
[5-2] W. G. Vandenberghe, B. Sorée, W. Magnus, M. V. Fischetti, A. S. Verhulst, and G. Groeseneken, - Int. Electron Devices Meet. 2011, 5.3.1 - 5.3.4.

 
 
 
 
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