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作者(中文):吳冠德
作者(外文):Wu, Kuan Te
論文名稱(中文):應用能帶工程電荷捕捉層及無接面以改善複晶矽奈米線快閃記憶體元件之操作特性
論文名稱(外文):Improved Operation Characteristics in Poly-Si Nanowire Flash Memory Devices with Junctionless and Bandgap-Engineered Trapping Layer
指導教授(中文):張廖貴術
指導教授(外文):Chang-Liao, Kuei-Shu
口試委員(中文):趙天生
劉致為
學位類別:碩士
校院名稱:國立清華大學
系所名稱:工程與系統科學系
學號:100011565
出版年(民國):102
畢業學年度:101
語文別:中文
論文頁數:91
中文關鍵詞:奈米線無接面高介電材料能帶工程快閃記憶體
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近年來,智慧型手機、平板電腦、輕薄型筆記型電腦等3C產品日漸普及,進而影響了整個記憶體產業的市場,造成擁有低功率消耗、元件密度高、可攜式條件等特性的快閃記憶體的需求量大幅上升。然而,在元件日漸微縮的趨勢下,平面式元件微縮空間有限,造成元件密度難增且製程難度跟著大幅的提升,因此如何不損電性又要提高元件密度為目前最重要的課題之一。有些解決方法已漸漸被提出,如高介電常數材料的應用、奈米線通道的結構、無接面快閃記憶體元件的應用等等。本篇論文以無接面奈米線通道式快閃記憶體元件為主軸,輔以高介電常數材料作能帶工程的應用,加以研究並探討電性的表現。
第一個實驗首次將高介電常數和無接面作結合應用在快閃記憶體元件上。本實驗中,以二氧化鉿和具氧化鉿鋁/二氧化鉿堆疊的結構作為電荷捕捉層,製作在無接面奈米線通道式的快閃記憶體元件上,並與電荷反轉式奈米線通道式快閃記憶體元件做比較。無接面元件在寫入速度和可靠度特性的表現上都具有較佳的表現,唯抹除速度較電荷反轉式元件緩慢,而具氧化鉿鋁/二氧化鉿堆疊的結構也能有效提升元件的電荷保持力特性。
第二個實驗中以二氧化鉿/氮化矽堆疊的結構作為電荷捕捉層,製作在無接面奈米線通道式的快閃記憶體元件上,並與電荷反轉式奈米線通道式快閃記憶體元件做比較。無接面元件仍維持了較佳的寫入速度和可靠度特性,且在抹除速度方面也能有所提升,和電荷反轉式元件已可相互比擬。
第三個實驗研襲第二章使用的電荷捕捉層,並與普遍較為常見的氮化矽作電荷捕捉層,同樣的製作在無接面奈米線通道式的快閃記憶體元件上,並與電荷反轉式奈米線通道式快閃記憶體元件做比較。可以發現除了無接面元件仍維持較佳的電性表現外,堆疊式的電荷捕捉層也能對各種電性表現有改善的效果。
目錄
摘要 I
致謝 III
目錄 V
表目錄 VII
圖目錄 VIII
第一章 序論 1
1.1 快閃記憶體元件 1
1.1.1 浮動閘極式快閃記憶體元件 1
1.1.2 電荷捕陷式快閃記憶體元件 2
1.2 多晶矽薄膜電晶體 3
1.3 多向式閘極結構與奈米線通道式快閃記憶體元件 4
1.4 高介電係數材料與能帶工程之介紹 5
1.4.1高介電係數材料 6
1.4.2能帶工程 7
1.5 無接面快閃記憶體元件介紹 8
1.6 各章摘要 9
第二章 快閃記憶體元件製程與操作方法 17
2.1 奈米線通道式快閃記憶體元件製程 17
2.1.1 傳統反轉層元件 17
2.1.2 無接面元件 18
2.2 快閃記憶體元件寫入與抹除方法 18
2.2.1 CHEI通道熱電子注入寫入 19
2.2.2 F-N穿隧寫入 19
2.2.3 F-N穿隧抹除 20
2.3 快閃記憶體元件可靠度特性 21
第三章 二氧化鉿和具氧化鉿鋁/二氧化鉿堆疊的電荷捕捉層應用在奈米線無接面之快閃記憶體元件特性研究 34
3.1 研究動機與背景 35
3.2 實驗 36
3.3 結果與討論 36
3.3.1 元件汲極電流對閘極電壓作圖 36
3.3.2 元件寫入與抹除特性 37
3.3.3 元件可靠度特性 38
3.3 結論 38
第四章 具二氧化鉿/氮化矽堆疊的電荷捕捉層應用在奈米線無接面之快閃記憶體元件特性研究 47
4.1 研究動機與背景 47
4.2 實驗 48
4.3 結果與討論 48
4.3.1 元件汲極電流對閘極電壓作圖 48
4.3.2 元件寫入與抹除特性 49
4.3.3 元件可靠度特性 50
4.4 結論 51
第五章 單層氮化矽和具二氧化鉿/氮化矽堆疊的電荷捕捉層應用在奈米線無接面之快閃記憶體元件特性研究 61
5.1 研究動機與背景 62
5.2 實驗 63
5.3 結果與討論 63
5.3.1 元件汲極電流對閘極電壓作圖 63
5.3.2 元件寫入與抹除特性 64
5.3.3 元件可靠度特性 67
5.4 結論 69
第六章 結論 85
參考文獻 88
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