此篇論文提出詳細的SAR ADCs設計流程，並在時域與頻域上分別討論設計時所需瞭解之電路運作原理，同時利用直觀的方式配合電路模擬軟體完成了整體SAR ADC之設計與佈局。實際設計流程則利用相對於傳統SAR ADC在比較過程上更加省電的合併電容開關式架構分別完成兩顆SAR ADC的設計。十二位元，低速之同步SAR ADC的設計上提出了簡單的數位控制邏輯，並利用低回踢雜訊比較器提升其有效位元數；另外，十位元，中速之非同步SAR ADC的設計上則提出了改良式動態D型暫存器解決了動態D型暫存器在數位邏輯上的錯誤，同時也利用低回踢雜訊比較器降低可能發生之錯誤。
十二位元，低速之同步SAR ADC的全範圍輸入電壓(V_FS)可達2*V_DD的95%，且在奈奎氏取樣率下可得有效位元數9.68，其FoM可達62(fJ/Con.-step)，其他較低之輸入頻率也皆能得到9.7以上的解析度。此外，在同樣量測環境下，各別量測不同晶片可得其有效位元數最低皆可達9.61，證實了製程偏移對於此電路架構的影響並不大。
十位元，中速之非同步SAR ADC的全範圍輸入電壓(V_FS)可達2*V_DD的95%，降速至3MHz後在奈奎氏取樣率下可得有效位元數8.73，其FoM可達88(fJ/Con.-step)，其他輸入頻率也皆能得到8.64以上的解析度。最後，各別量測不同晶片可得其有效位元數最低可達8.66，同時也證實了此晶片的重現性與可靠度。

This thesis elaborated a design process of SAR ADCs, which discussed the fundamental circuit theorems in SAR ADCs by aspects of time and frequency domains and meanwhile, completing the layout and the design of whole ADC by the circuit simulation tools with an easy intuition. Relative to the conventional SAR ADC, the merged capacitor switching based SAR ADCs are more power efficient. Therefore, the thesis implemented two SAR ADCs which based on the merged capacitor switching algorism, including a 12-bit 100k-S/s synchronous SAR ADC, which contained a simple digital control logic and a low-kickback noise comparator to enhance the ENOB, and a 10-bit 10M-S/s asynchronous SAR ADC, which modifying the dynamic D type Flip-Flop to avoid the error in asynchronous clock generator and also used a low-kickback noise comparator to decrease the possibility of the wrong comparative process.
The input signal range of the 12-bit 100k-S/s synchronous SAR ADC could achieve 95% of 2V_DD. The ENOB at Nyquist rate is 9.68, and the FoM is 62(fJ/Con.-step). Furthermore, the ENOB at lower frequency input of ADCs could all achieve over 9.7. In the other hand, the ENOB of the other chips at Nyquist rate are all above 9.61, which verified the influence of the process variation in those chips is small.
The input signal range of the 10-bit 10M-S/s asynchronous SAR ADCs could also achieve 95% of 2V_DD. After decreasing the sampling rate to 3M-S/s, the ENOB at Nyquist rate is 8.73, and the FoM is 88(fJ/Con.-step). Furthermore, the ENOB at lower frequency input of ADCs could all achieve over 8.64. In the other hand, the ENOB of the different chips at Nyquist rate are all above 8.66, which proved that the reliable and repeatable of these chips is well.

致謝 i
中文摘要 ii
目錄 iv
圖目錄 viii
表目錄 xiii
第一章 緒論 1
1.1 研究動機 1
1.2 研究背景 2
1.3 類比數位轉換器特性參數[17] 3
1.3.1. 輸入頻率(Input Rate)與取樣頻率(Sampling Rate) 4
1.3.2. 量化雜訊(Quantization Noise) 5
1.3.3. 解析度(Resolution) 5
1.3.4. 微分非線性誤差(Differential Nonlinearity DNL) 5
1.3.5. 積分非線性誤差(Integral Nonlinearity INL) 6
1.3.6. 直流偏差 (DC offset) 6
1.3.7. 增益偏差(Gain Error) 7
1.3.8. 非線性誤差(Nonlinearity Error) 8
1.3.9. 訊號雜訊比(Signal to Noise Ratio) 8
1.3.10. 無雜散動態範圍(Spurious Free Dynamic Range) 9
1.3.11. 有效位元數(Effective Resolution of Bits) 9
1.3.12. 效能參數(Figure of Merit) 10
1.4 論文章節組織 10
第二章 連續漸近式類比數位轉換器概論 11
2.1 連續漸近式類比數位轉換器的基本架構[18] 11
2.2 取樣電路[19] 12
2.2.1 電晶體開關的導通電阻 12
2.2.2 電荷注入效應(Charge Injection) 16
2.2.3 時脈耦合效應(Clock Feedthrough) 17
2.2.4 熱雜訊(Thermal Noise) 18
2.2.5 取樣電路設計總結 18
2.3 類比數位轉換器 19
2.3.1 二位元權重數位類比轉換器[21] 19
2.3.2 寄生電容與單位電容設計 20
2.4 比較器 20
2.4.1. 輸入電壓偏移(Input Offset) 20
2.4.2. 回踢雜訊(Kickback Noise) 21
2.5 連續漸近式暫存器[22] 22
第三章 電路設計與實現 24
3.1 全差動式連續漸進式類比數位轉換器 24
3.1.1. 差動訊號取樣與寄生電容效應 24
3.1.2. 傳統全差動式SAR ADC 比較過程 26
3.2 電路架構選擇 28
3.2.1 合併電容開關式連續漸進類比數位轉換器 28
3.2.2 全差動式電容架構比較 31
3.3 十二位元，低速之同步時脈低功耗SAR ADC設計 32
3.3.1. 靴帶式開關[20] 33
3.3.2. 比較器 39
3.3.3. 同步時脈產生器 45
3.3.4. 開關控制邏輯 47
3.3.5. 電容陣列與佈局考量 51
3.3.6. 參考電壓開關設計與轉換暫態模擬 54
3.3.7. ADC佈局 58
3.4 十位元，中速之非同步低功耗SAR ADC設計 60
3.4.1. 靴帶式開關 61
3.4.2. 比較器 63
3.4.3. 非同步時脈產生器 64
3.4.4. 開關控制邏輯 71
3.4.5. 電容陣列與佈局考量 74
3.4.6. 參考電壓開關設計與轉換暫態模擬 79
3.4.7. ADC佈局 77
第四章 模擬結果 81
4.1 十二位元，低速之同步時脈低功耗SAR ADC 81
4.1.1. 佈局前模擬 81
4.1.2. 佈局後模擬 84
4.1.3. 模擬結果整理與佈局前後比較 86
4.2 十位元，中速之非同步時脈低功耗SAR ADC 88
4.2.1. 佈局前模擬 88
4.2.2. 佈局後模擬 91
4.2.3. 模擬結果整理與佈局前後比較 93
第五章 量測環境與結果 95
5.1 量測環境規劃 95
5.1.1. 量測環境 95
5.1.2. 量測規劃與架設 97
5.2 十二位元，低速之同步時脈低功耗SAR ADC量測結果 98
5.2.1. 靜態參數量測 98
5.2.2. 動態參數量測 99
5.2.3. 量測結果與文獻比較 104
5.3 十位元，中速之非同步時脈低功耗SAR ADC量測結果 106
5.3.1. 靜態參數量測 107
5.3.2. 動態參數量測 108
5.3.3. 量測結果與文獻比較 112
第六章 結論與未來展望 114
6.1. 結論 114
6.2. 未來展望 115
參考文獻 117

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