使用氮化矽做電荷儲存層之電荷陷阱式快閃記憶體，許多問題無法滿足元件微縮發展的趨勢，因此利用高介電係數材料取代氮化矽結構作為電荷儲存層之電荷陷阱式快閃記憶體元件是未來發展的趨勢。然而傳統以二氧化鉿作為儲存層的TAHOS元件結構，亦存在許多問題而無法滿足元件特性上的要求，因此便引進了堆疊式電荷儲存層結構以提升元件操作效能。本實驗使用核研所浸潤式離子佈植機，以不同的氮摻雜時間及退火溫度，氮化元件的高介電係數材料。研究主要是利用氮化後的特性，配合堆疊的結構，藉著電荷陷阱密度的多寡、能階大小的改變、K值影響分壓的不同、陷阱能階等種種特性，達成各項操作特性的提升。本論文研究的方向主要分為下列三大方向:
1.利用PIII電漿離子將氮摻雜於氧化鉿鋁與二氧化鉿之多層電荷儲存層的技術，探討改變氮化時間且相同退火溫度處理後，氮元素在氧化鉿鋁與二氧化鉿之多層電荷儲存層中的分佈情況對於電荷陷阱式快閃記憶體操作特性的影響。實驗結果顯示，氮摻雜於氧化鉿鋁與二氧化鉿之多層電荷儲存層中最佳的氮化時間為30分鐘，在寫入/抹除速度、電荷保持力與耐力方面，都有明顯提升。
2.利用PIII電漿離子的技術，將前一章中最佳的氮摻雜時間，應用於氧化鉿鋁與二氧化鉿之多層電荷儲存層中，再配合不同的退火溫度處理後，釐清氮元素在氧化鉿鋁與二氧化鉿之多層電荷儲存層中的分佈情況，且探討此氮元素分佈狀況對電荷陷阱式快閃記憶體操作特性的影響。由實驗得知，利用PIII電漿離子氮摻雜30分鐘且經過900℃/30秒退火溫度處理後，氮元素分佈在氧化鉿鋁中的量會比分佈在二氧化鉿中還要多，在寫入/抹除速度、電荷保持力與耐力方面都會有比較好的表現。
3.本章以Si3N4/Al2O3/HfO2堆疊式電荷儲存層結構為基礎，分成兩個實驗部分，第一部分實驗為：改變Si3N4/Al2O3/HfO2堆疊式電荷儲存層之中間阻擋層Al2O3的厚度，探討此變化對電荷陷阱式快閃記憶體操作特性的影響，且找出最佳化之Si3N4/Al2O3/HfO2堆疊式電荷儲存層之中間阻擋Al2O3厚度的參數。由實驗結果得知，Si3N4/Al2O3/HfO2堆疊式電荷儲存層之中間阻擋層Al2O3為30Å的厚度時，在操作寫入/抹除時，第一層Si3N4與第三層HfO2之電荷儲存層對於捕捉載子的情況可以發揮最大的效應，使得寫入/抹除速度最快，且此厚度對於電荷保持力與耐力方面也會比較優異；第二部分實驗為：利用本章第一部分實驗中，Si3N4/Al2O3/HfO2堆疊式電荷儲存層之中間阻擋層Al2O3最佳化之30Å的厚度，繼續作延伸與探討，使用Si3N4/Al2O3/HfO2堆疊式電荷儲存層之中間阻擋層Al2O3最佳化的參數，改變Si3N4/Al2O3/HfO2堆疊式電荷儲存層中Si3N4與HfO2兩層電荷儲存層的厚度，探討此堆疊結構對電荷陷阱式快閃記憶體操作特性的影響。實驗結果顯示，第一層Si3N4的厚度為30Å與第一層Si3N4的厚度為40Å相較起來，30Å的Si3N4會使得堆疊式電荷儲存層之中間阻擋層Al2O3比較靠近穿隧氧化層，因此對於寫入/抹除速度會比較有利，且在電荷保持力與耐力方面此結構之厚度的表現還是較佳。
由實驗結果可發現，引進PIII電漿離子氮化技術，使用最佳化的氮摻雜時間與最佳化的退火溫度處理配合之，應用於氧化鉿鋁與二氧化鉿電荷儲存層，將有效地提升電荷陷阱式快閃記憶體中各種操作特性；另外，在Si3N4/Al2O3/HfO2堆疊式電荷儲存層結構中，Si3N4/Al2O3/HfO2堆疊式電荷儲存層之中間阻擋層Al2O3與第一層Si3N4之電荷儲存層有最佳化厚度之參數，此參數對於電荷陷阱式快閃記憶體可以有最好的操作特性。

摘要 I
致謝 III
目錄 V
圖目錄 VII
表目錄 XIII
第 一 章 序論 1
1.1 前言 1
1.2 快閃記憶體面臨的問題 2
1.3 電荷陷阱式快閃記憶體(Charge Trap Flash)的結構與優缺點 2
1.4 High-k材料應用於快閃記憶體的儲存層上 4
1.5 氮化二氧化鉿材料應用於快閃記憶體的儲存層上 5
1.6 各章摘要 6
第 二 章 快閃記憶體元件操作方法 13
2.1 寫入與抹除方法 13
2.1.1 通道熱電子注入 13
2.1.2 F-N穿隧寫入 14
2.1.3 F-N穿隧擦拭 14
2.2 電荷保持力(retention) 15
2.3 耐力(endurance) 16
第 三 章 實驗規畫及元件製程 24
3.1 實驗規劃 25
3.2 電晶體元件製程 25
3.2.1 電晶體前段製程 25
3.2.2 成長穿隧氧化層 26
3.2.3 沈積電荷儲存層及阻擋氧化層 26
3.2.4 氮化電荷儲存層及阻擋氧化層 27
3.2.5 後段製程 27
3.3 電漿浸潤式離子佈植(PIII) 28
3.3.1 電漿產生原理 28
3.3.2 電子迴旋共振微波電漿源(ECR microwave plasma source) 29
第 四 章 利用PIII氮化氧化鉿鋁與二氧化鉿應用於多層電荷儲存層對電荷陷阱式快閃記憶體特性研究 32
4.1 研究背景與目的 33
4.2 實驗規畫與製程 34
4.3 實驗結果與討論 35
4.3.1 物性分析比較 36
4.3.2 寫入特性比較 37
4.3.3 抹除特性比較 39
4.3.4 常溫與高溫電荷保持力特性比較 40
4.3.5 耐力特性比較 41
4.4 結論 42
第 五 章 利用PIII相同摻雜濃度配合不同退火溫度應用於多層電荷儲存層對電荷陷阱式快閃記憶體特性研究 56
5.1 研究背景與目的 57
5.2 實驗規畫與製程 57
5.3 實驗結果與討論 59
5.3.1 物性分析比較 59
5.3.2 寫入特性比較 61
5.3.3 抹除特性比較 63
5.3.4 常溫與高溫電荷保持力特性比較 65
5.3.5 耐力特性比較 66
5.4 結論 66
第 六 章 能帶工程於電荷儲存層之中間阻擋層最佳化應用於電荷陷阱式快閃記憶體元件 82
6.1 研究背景與目的 83
6.2 實驗規劃與製程 84
6.3 實驗結果與討論 85
6.3.1 寫入特性比較 85
6.3.2 抹除特性比較 87
6.3.3 常溫與高溫電荷保持力特性比較 89
6.3.4 耐力特性比較 89
6.4 結論 90
第 七 章 106
結論與建議 106
7.1 結論 106
7.2 建議 107
參考文獻 109

[1]Harry Pon , et al. , "Technology scaling impact on NOR and NAND flash memories and their applications," in Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on, 2006, pp. 697-700.
[2]Min She, “semiconductor Flash Memory Scaling” , University of California, Berkeley , Doctor of Philosophy , 2003.
[3]A. Paul, Ch. Sridhar, et al. , "Comprehensive Simulation of Program, Erase and Retention in Charge Trapping Flash Memories," in Electron Devices Meeting, 2006. IEDM '06. International, 2006, pp. 1-4.
[4]Y. N. Tan, et al. , "Over-erase phenomenon in SONOS-type flash memory and its minimization using a hafnium oxide charge storage Layer," Electron Devices, IEEE Transactions on, vol. 51, pp. 1143-1147, 2004.
[5]J. V. Houdt, et al. , "High-k materials for nonvolatile memory applications," in Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. 2005 IEEE International, 2005, pp. 234-239.
[6]T. Sugizaki, M. Kobayashi, et al. , "Novel multi-bit SONOS type flash memory using a high-k charge trapping layer," in VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on, 2003, pp. 27-28.
[7]Y. N. Tan, et al. , "High-k HfAlO charge trapping layer in SONOS-type nonvolatile memory device for high speed operation," in Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International, 2004, pp. 889-892.
[8]M. S. Joo, et al. , "Dependence of Chemical Composition Ratio on Electrical Properties of HfO2-Al2O3 Gate Dielectric," Japanese Journal of Applied Physics, vol. 42, p. L220.
[9]W.J. Zhu , et al. , "Effect of Al inclusion in HfO2 on the physical and electrical properties of the dielectrics," Electron Device Letters, IEEE, vol. 23, pp. 649-651, 2002.
[10]G. Molas et al. , "Thorough investigation of Si-nanocrystal memories with high-k interpoly dielectrics for sub-45nm node Flash NAND applications," in Electron Devices Meeting, 2007. IEDM 2007. IEEE International, 2007, pp. 453-456.
[11]Y. N. Tan, et al. , "Hafnium aluminum oxide as charge storage and blocking-oxide layers in SONOS-type nonvolatile memory for high-speed operation," Electron Devices, IEEE Transactions on, vol. 53, pp. 654-662, 2006.
[12]Z. L. Huo et al. , "Band Engineered Charge Trap Layer for highly Reliable MLC Flash Memory," in VLSI Technology, 2007 IEEE Symposium on, 2007, pp. 138-139.
[13]H. J. Yang, et al. , "Comparison of MONOS Memory Device Integrity When Using Hf1-x-yNxOy Trapping Layers With Different N Compositions," Electron Devices, IEEE Transactions on, vol. 55, pp. 1417-1423, 2008.
[14]J. Bu, et al. , "Retention reliability enhanced SONOS NVSM with scaled programming voltage," in Aerospace Conference Proceedings, 2002. IEEE, 2002, pp. 5-2383-5-2390 vol.5.
[15]M. H. White, et al. , "A low voltage SONOS nonvolatile semiconductor memory technology," Components, Packaging, and Manufacturing Technology, Part A, IEEE Transactions on, vol. 20, pp. 190-195, 1997.
[16]W.J. Tsai, et al. , "Data retention behavior of a SONOS type two-bit storage flash memory cell," in Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International, 2001, pp. 32.6.1-32.6.4.
[17]K. T. San, et al. , "Effects of erase source bias on Flash EPROM device reliability," Electron Devices, IEEE Transactions on, vol. 42, pp. 150-159, 1995.
[18]M. Chang, et al. , "Charge loss behavior of a metal-alumina-nitride-oxide-silicon-type flash memory cell with different levels of charge injection," Applied Physics Letters, vol. 93, pp. 232105-232105-3, 2008.
[19]J. R. Roth, Industrial Plasma Engineering-Volume 1: Principles, Institute of Physics Publishing, London, 1995.
[20]ITRS, Process Integration Devices and the structures , 2012 , pp. 35-37
[21]Hirotaka Hamamura, et al. , "Electron trapping characteristics and scalability of HfO2 as a trapping layer in SONOS-type flash memories," in Reliability Physics Symposium, 2008. IRPS 2008. IEEE International, 2008, pp. 412-416.
[22]P.H. Tsai, et al. , "Novel SONOS-Type Nonvolatile Memory Device With Optimal Al Doping in HfAlO Charge-Trapping Layer," Electron Device Letters, IEEE, vol. 29, pp. 265-268, 2008.
[23]Helen Grampeix, et al. , "Effect of Nitridation for High-K Layers by ALCVDTM in Order to Decrease the Trapping in Non Volatile Memories," ECS Transactions, vol. 11, pp. 213-225, September 28, 2007.
[24]G.D. Wilk, et al. , "High-K gate dielectrics: Current status and materials properties considerations," Journal of Applied Physics, vol. 89, pp. 5243-5275, 2001.
[25]Te-Chiang Liu, et al. , "Operation Characteristic of Charge-Trapping-type Flash Memory Device with Charge-trapping layer of stacked dielectrics, " July, 2008.
[26]S. Y. Wang, et al. , “Reliability And Processing Effects Of Band-gap Engineered SONOS (BE-SONOS) Flash Memory”, International Reliability Physics Symposium , 2007, page(s):171-176.
[27]K. H. Wu, et al. , “SONOS Device With Tapered Band-gap Nitride Layer”, Electron Device Letters, 2005, page(s):987-992.
[28]H.C. Chien, et al. , “Two-bit SONOS type Flash using a band engineering in the nitride layer”, Microelectronics. Eng., 2005, pp. 256.
[29]G. Zhang, et al. , “Spatial Distribution of Charge Traps in a SONOS-Type Flash Memory Using a High-k Trapping Layer”, IEEE Tran. on Electron Device Letters, 2007, page(s):3317-3324
[30]Zong-Hao Ye, et al. , "Enhanced Operation in Charge-Trapping Nonvolatile Memory Device With Si3N4/Al2O3/HfO2 Charge-Trapping Layer," Electron Device Letters, IEEE, vol. 33, pp. 1351-1353, 2012.
[31]Sandhya C., et al. , “Nitride Engineering and the effect of interfaces on charge trap flash performance and reliability” , International Reliability Physics Symposium ,2008 , page(s):406-411.
[32]G.Zhang, et al. , “Potential Well Engineering by Partial Oxidation of TiN for High-Speed and Low-Voltage Flash Memory with Good 125oC Data Retention and Excellent Endurance” , International Electron Device Meeting , 2009 , page(s):1-4.