在此篇論文的研究中，我們是第一個提出具全環繞式閘極與超薄主動層(2nm)N型無接面多晶矽薄膜電晶體的研究。在此研究中我們使用低溫多晶矽製程成功製造出擁有超薄主動層(2nm)的N型無接面多晶矽薄膜電晶體，在此多晶矽主動層中我們利用氧化薄化方式將主動層薄化去取代傳統直接沉積一薄層主動層的方式。氧化薄化方式比起直接沉積薄主動層可以得到較大的晶粒與較少的晶界。此元件展現出極佳的電性，像是SS達到接近理想值的 61mV/dec以及極佳的開關特性，這主要是因為元件夠薄使的閘極擁有很好的控制能力。另外此元件在短通道效應的抑制上展現出極佳的能力，經實測，其DIBL值為6mV/V。由於元件相當薄，我們有去做元件厚度誤差研究，發現其誤差值非常小，這足以證明這種氧化薄化的方式不僅製成簡單並且可以相當穩定的去應用到現今以及未來的製程科技上面。
在此篇研究中首先是專注在元件製成以及基礎元件特性分析，接下來為了測試此元件在應用面的廣度，我們會對此元件進行多種可靠度分析，像是在高溫下此元件在電性上的劣化反應、在高壓下的崩潰反應以及熱載仔對元件產生的劣化反應。
在高溫可靠度的部分，此元件有3個特色: 1) Vth隨著溫度增高劣化幅度相當小，這主要是因為通道夠薄使的元件能處在接近完全空乏的狀態。2) SS再隨溫度變化的同時仍能持續接近理想值，這主要是因為其通道夠薄，薄到有接近單晶的行為。3) 在漏電的部分，此元件在隨著溫度上升的過程中仍能保持比起其他元件小的漏電，這主因是因為元件夠薄產生量子侷限效應所導致。
在高壓崩潰機制的可靠度分析上，此研究利用傳統電晶體當其對照組，去比較無接面電晶體與傳統有PN接面的電晶體在高壓上的反應，此研究並搭配3D結構的TCAD元件模擬去看其電場在元件中的分布，經實測發現在通道關閉的狀態時，具全環繞式閘極的無接面電晶體 (JL-GAA TFT) 的崩潰電壓為53.4 V此數值大於具全環繞式閘極的傳統PN接面電晶體 (IM-GAA TFT)。由此可知此無接面電晶體在未來有機會應用在高壓元件領域。除此之外，由模擬中可知，此無接面電晶體因為沒有PN接面，在通道開啟時其電場是均勻分布在整個通道，其行為就像是一個電阻，所以可以耐壓。
在熱載子對元件產生的劣化反應分析中，我們對JL-GAA, JL-Planar, IM-GAA and IM-Planar TFTs進行分析，由實驗中發現，JL-Planar TFT比起IM-Planar TFT在熱載子對元件產生的劣化反應分析中擁有較佳的可靠度，JL-Planar TFT因為沒有內建電場，所以無接面電晶體在元件中的電場比起傳統PN接面電晶體來的低，鑒於以上的論述，JL-Planar TFT擁有較低的熱載子對元件產生的劣化行為。
在此篇研究中，我們首先提出具全環繞式閘極與超薄主動層(2nm)N型無接面多晶矽薄膜電晶體。其展現出了極佳的電性、Vth在高溫時僅有相當輕微的劣化、相當好的耐壓能力以及理想的抗熱載子對元件產生的劣化反應。

This work is the first time to demonstrate the gate-all-around (GAA) n-channel junctionless (JL) polycrystalline silicon (poly-Si) thin-film-transistor (TFT) with 2 nm ultra-thin channel. Using low temperature poly-Si (LTPS) to fabricate JL-GAA TFTs with ultra-thin channel are successfully fabricated by oxidation thinning process. This work use the dry oxidation to form the ultra-thin channel instead of directly depositing the thin-film as the poly-Si channel in JL TFTs. The dry oxidation thinning method could get larger grain size and less grain boundary than directly depositing the thin-film. The sub-threshold swing (SS) is 61mV/decade, and the on/off current ratio is close to 108 due to the excellent gate controllability and ultra-thin channel. The JL-GAA TFTs have a low DIBL value of 6mV/V, indicating greater suppression of the short channel effect than in JL-Planar TFTs. The cumulative distribution of electrical parameters in JL-GAA is small. Therefore, the proposed JL-GAA TFTs of excellent device characteristics along with simple fabrication are highly promising for future (system-on-panel) SOP and system-on-chip (SOC) applications. This process is simple and compatible with existing CMOS processes.
Firstly, this work focuses on the device process and basic device characteristics analysis. Next, the reliability analysis of JL-GAA TFT include high temperature performance, breakdown mechanism and hot carrier stress are investigated in this thesis.
In the high temperature reliability analysis, the JL-GAA TFT with ultra-thin channel indicates three characteristics: 1) The threshold volt-age (Vth) is less sensitive to temperature due to thinner channel thickness. 2) The subthreshold slope (SS) is nearly close to the idea values with increasing temperature due to the poly-Si channel approaching to single crystal. 3) The OFF-state current is lowest as temperature rises, owing to quantum confinement effect.
In the high voltage breakdown mechanism analysis, the breakdown voltage (VBD) and breakdown mechanism of JL poly-Si TFT were compared to the conventional inversion-mode (IM) TFT using fabricated devices and 3D quantum hydrodynamic transport device simulation. The JL TFT shows excellent breakdown characteristics, the off-state VBD of 53.4V is several times larger than VBD of 9.5V in IM TFT with same device size. JL devices have large potential for high voltage power MOS devices and circuits application. The analysis of electric field distributions in on-state show that the channel of JL devices can equally share the voltage like a resistor, because there are no junctions formed between channel and source/drain.
In the hot carrier stress analysis, the degradation behaviors after hot-carrier stress of JL-GAA, JL-Planar, IM-GAA and IM-Planar poly-Si TFTs are investigated. JL-Planar device presents better reliability than IM-Planar device after hot carrier stress. The lesser degradation is due to the peaks of lateral electric field of junctionless device is lower than inversion mode device.
In this study, we demonstrate that JL-GAA TFT with 2nm ultra-thin channel shows excellent electrical characteristics. And we find that the threshold voltage of JL-GAA TFT is less sensitive to temperature, the breakdown voltage in JL-GAA TFT is several times larger than IM-GAA TFT and JL-Planar presents better reliability than IM-Planar after hot carrier stress.

中 文 摘 要 i
Abstract iii
Acknowledge v
Contents vi
Table Captions vii
Figure Captions viii
Chapter 1 - 1 -
Introduction - 1 -
1-1 Introduction of Junctionless Device - 1 -
1-2 Motivation - 3 -
1-3 Thesis Organization - 4 -
Chapter 2 - 16 -
Junctionless Mechanism - 16 -
2-1 Basic Principle of Junctionless Transistor - 16 -
2-2 Short Channel Effect (SCE) in Junctionless transistor - 22 -
2-3 Threshold voltage in junctionless transistor - 25 -
2-4 Quantum Confinement Effect in TFT with Ultra-Thin Body - 27 -
Chapter 3 - 29 -
Device Fabrication and Device Simulation - 29 -
3-1 Device Fabrication Process - 29 -
3-2 Device Simulation - 31 -
Chapter 4 - 33 -
Characteristics Analysis - 33 -
4-1 TEM Images Analysis - 33 -
4-2 Device Characteristics Analysis - 35 -
4-3 Quantum Confinement Effect in Threshold Voltage - 40 -
4-4 Conclusion - 42 -
Chapter 5 - 43 -
Reliability Study - 43 -
5-1 Temperature Performance - 43 -
5-1-1 Introduction - 43 -
5-1-2 Results and Discussions - 43 -
5-1-3 Conclusion - 45 -
5-2 Breakdown Discussion - 52 -
5-2-1 Introduction - 52 -
5-2-2 Results and Discussions - 53 -
5-2-3 Conclusion - 55 -
5-3 Hot Carrier Stress Discussion - 61 -
5-3-1 Introduction - 61 -
5-3-2 Results and Discussions - 62 -
5-3-3 Conclusion - 62 -
Chapter 6 - 69 -
Conclusion - 69 -
Reference - 71 -

Chapter 1

1-1. J. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A. M. Kelleher, B. McCarthy, and R. Murphy, “Nanowire transistors without junctions,” Nat. Nanotechnol., vol. 5, no. 3, pp. 225–229, Mar. 2010.
1-2. Hung-Bin Chen, Yung-Chun Wu, Chun-Yen Chang, Ming-Hung Han, Nan-Heng Lu, and Ya-Chi Cheng, "Performance of GAA poly-Si Nanosheet (2nm) channel of Junctionless Transistors with ideal Subthreshold Slope", in VLSI Symp. Tech. Dig., Kyoto, Japan, Jun., 2013.
1-3. Shinji Migita, Yukinori Morita, Meishoku Masahara, and Hiroyuki Ota, “Electrical Performances of Junctionless-FETs at the Scaling Limit (LCH = 3 nm),” Electron Devices Meeting (IEDM), 2012 IEEE International, 2012,
1-4. Horng-Chih Lin, Senior Member, IEEE, Cheng-I Lin, Zer-Ming Lin, Bo-Shiuan Shie, and Tiao-Yuan Huang, “Characteristics of Planar Junctionless Poly-Si Thin-Film Transistors With Various Channel Thickness,” IEEE Electron Device Lett.,vol. 60, pp. 1142–1148, 2013.
1-5. H. Tanaka, M. Kido, K. Yahashi, M. Oomura, R. Katsumata, M. Kito, Y. Fukuzumi, M. Sato, Y. Nagata, Y. Matsuoka, Y. Iwata, H. Aochi, and A. Nitayama, “Bit cost scalable technology with punch and plug process for ultra high density Flash memory,” in VLSI Symp. Tech. Dig., 2007, pp. 14–15.
1-6. H. T. Lue, T. H. Hsu, Y. H. Hsiao, S. P. Hong, M. T. Wu, F. H. Hsu, N. Z. Lien, S. Y. Wang, J. Y. Hsieh, L. W. Yang, T. Yang, K. C. Chen, K. Y. Hsieh, and C. Y. Lu, “A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND flash using junction-free buried channel BE-SONOS device,” in VLSI Symp. Tech. Dig., pp. 131–132, 2010.
1-7. Bio KIM, Seung-Hyun LIM, Dong Woo KIM, Toshiro NAKANISHI, Sangryol YANG, Jae-Young AHN, HanMei CHOI, Kihyun HWANG, Yongsun KO, Chang-Jin KANG, “Investigation of ultra thin polycrystalline silicon channel for vertical NAND flash”, Reliability Physics Symposium (IRPS), IEEE International,., pp. 126-129, 2011.
1-8. J. P. Colinge, C. Lee, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, A. Kranti, R. Yu, Junctionless Transistors: Physics and Properties, Semiconductor-On-Insulator Materials for Nanoelectronics Applications, Springer, Verlag Berlin Heidelberg, pp. 187–200, 2011.

Chapter 2

2-1. J.P. Colinge, Semiconductor-On-Insulator Materials for NanoElectronics Applications, chapter 10, pp.187, 2011.
2-2. P. Razavi, G. Fagas, I. Ferain, R. Yu, S. Das, and J. Colinge, “Influence of channel material properties on performance of nanowire transistors,” J. Appl. Phys., vol. 111, no. 12, pp. 124509-1–124509-8, Jun. 2012.
2-3. R. Trevisoli, R. Doria, M. de -Souza, and M. Pavanello, “Threshold voltage in junctionless nanowire transistors,” Semicond. Sci. Technol., vol. 26, p. 105 009, Oct. 2011.
2-4. Xiaojun Guo, Tomoyuki Ishii, and S. R. P. Silva, “Improving Switching Performance of Thin-Film Transistors in Disordered Silicon,” EDL, 2008, vol. 29, pp. 588–591.

Chapter 3

3-1. User’s Manual for Synopsys Sentaurus Device

Chapter 4

4-1. J. P. Colinge, C. Lee, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, A. Kranti, R. Yu, Junctionless Transistors: Physics and Properties, Semiconductor-On-Insulator Materials for Nanoelectronics Applications, Springer, Verlag Berlin Heidelberg, pp. 187–200, 2011.
4-2. N. Singh, F. Y. Lim, W. W. Fang, S. C. Rustagi, L. K. Bera, A. Agarwal, C. H. Tung, K. M. Hoe, S. R. Omampuliyur, D. Tripathi, A. O. Adeyeye, G. Q. Lo, N. Balasubramanian, and D. L. Kwong, "Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance", in IEDM Tech. Dig., 2006, pp. 1–4.
4-3. R. Trevisoli, R. Doria, M. de -Souza, and M. Pavanello, “Threshold voltage in junctionless nanowire transistors,” Semicond. Sci. Technol., vol. 26, p. 105 009, Oct. 2011.
4-4. R. D. Chang and J. R. Tsai, “Loss of phosphorus due to segregation at Si/SiO2 interfaces: Experiments and modeling,” J. Appl. Phys., vol. 103, no. 5, pp. 053507-1–053507-6, Mar. 2008.
4-5. R. D. Chang, C. C. Ma, and J. R. Tsai, “Dose loss of phosphorus due to interface segregation in silicon-on-insulator substrates,” J. Vac. Sci. Technol. B, Microelectron. Nanom. Struct., vol. 28, no. 6, pp. 1158–1163, Nov. 2010.

Chapter 5

5-1. J. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A. M. Kelleher, B. McCarthy, and R. Murphy, “Nanowire transistors without junctions,” Nat. Nanotechnol., vol. 5, no. 3, pp. 225–229, Mar. 2010.
5-2. Chi-Woo Lee, Adrien Borne, Isabelle Ferain, Aryan Afzalian, Member, IEEE, Ran Yan, Nima Dehdashti Akhavan, Pedram Razavi, and Jean-Pierre Colinge, “High-Temperature Performance of Silicon Junctionless MOSFETs”, ED, vol. 57, pp. 620 – 624, 2010.
5-3. J. H. Schon and B. Batlogg, “Modeling of the temperature dependence of the field-effect mobility in thin film devices of conjugated oligomers”, APL, vol. 74, pp. 260, 1999.
5-4. Synopsys Santaurus Device.
5-5. Xiaojun Guo, Tomoyuki Ishii, and S. R. P. Silva, “Improving Switching Performance of Thin-Film Transistors in Disordered Silicon,” EDL, 2008, vol. 29, pp. 588–591.
5-6. S. M. Sze, and K. K. Ng, Physics of Semiconductor Devices. New Jersey: Wiley- Interscience, 2007.
5-7. C. Hu, Dig. Tech. Pap. - Symp. VLSI Technol. 2004, 4.
5-8. T. Skotnicki, J. A. Hutchby, T.-J. King, H.-S. P. Wong, and F. Boeuf, IEEE Circuits Devices Mag. 21, 16 (2005).
5-9. G. Roy, A. R. Brown, F. Adamu-Lema, S. Roy, and A. Asenov, “Simulation Study of Individual and Combined Sources of Intrinsic Parameter Fluctuations in Conventional Nano-MOSFETs,” IEEE Trans, Electron Devices 53, 3063 (2006).
5-10. G. D. Wilk, R. M. Wallace, and J. M. Anthony, J. Appl. Phys. 89, 5243 (2001).
5-11. D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King, J. Bokor, and C. Hu, IEEE Trans. Electron Device 47, 2320 (2000).
5-12. C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, and J. P. Colinge, “Junctionless multigate field-effect transistor,” Appl. Phys. Lett. 94, 053511 (2009).
5-13. J. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A. M. Kelleher, B. McCarthy, and R. Murphy, “Nanowire transistors without junctions,” Nat. Nanotechnol., vol. 5, no. 3, pp. 225–229, Mar. 2010.
5-14. J. P. Colinge, C.-W. Lee, I. Ferain, N. D. Akhavan, R. Yan, R. Razavi, R. Yu, A. N. Nazarov, and R. T. Doria,” Reduced electric field in junctionless transistors,” Appl. Phys. Lett. 96, 073510 (2010).
5-15. Horng-Chih Lin, Senior Member, IEEE, Cheng-I Lin, Zer-Ming Lin, Bo-Shiuan Shie, and Tiao-Yuan Huang, “Characteristics of Planar Junctionless Poly-Si Thin-Film Transistors With Various Channel Thickness,” IEEE Electron DeviceLett.,vol. 60, pp. 1142–1148, 2013..
5-16. C.-J. Su, T.-I Tsai, Y.-L. Liou, Z.-M. Lin, H.-C. Lin, and T.-S. Chao, IEEE Electron Device Lett. 32, 521 (2011).
5-17. R. Rios, A. Cappellani, M. Armstrong, A. Budrevich, H. Gomez, R. Pai, N. Rahhal-orabi, and K. Kuhn, ” Comparison of Junctionless and Conventional Trigate Transistors With Lg Down to 26 nm,” IEEE Electron Device Lett. 32, 1170 (2011).
5-18. User’s Manual for Synopsys Sentaurus Device.
5-19. M. -F. Hung, Y. -C. Wu, and Z. -Y. Tang, “High-performance gate-all-around polycrystalline silicon nanowire with silicon nanocrystals nonvolatile memory,” Appl. Phys. Lett. 98, 162108 (2011).
5-20. H. B. Chen, Y. C. Wu, C. Y. Chang, M. H. Han, N. H. Lu, Y. C Cheng, “Performance of GAA poly-Si Nanosheet (2nm) channel of Junctionless Transistors with ideal Subthreshold Slope,” Dig. Tech. Pap. Symp. VLSI Technol. 232 (2013).
5-21. J. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A. M. Kelleher, B. McCarthy, and R. Murphy, “Nanowire transistors without junctions,” Nat. Nanotechnol., vol. 5, no. 3, pp. 225–229, Mar. 2010.
5-22. Jong Tae Park, Jin Young Kim and Jean Pierre Colinge, “Negative-bias-temperature-instability and hot carrier effects in nanowire junctionless p-channel multigate transistors”, APL, vol. 100, pp. 083504-1 – 083504-3, 2012.
5-23. Yung-Chun Wu, Ting-Chang Chang, Po-Tsun Liu, and Li-Wei Feng, “Degradation Behaviors of Trigate Nanowires Poly-Si TFTs with NH3 Plasma Passivation under Hot-Carrier Stress”, ECS, vol. 10, pp. H235-H238, 2007.