本研究提出的n-通道和p-通道雙晶型多晶矽鰭式場效應記憶體（FinFET）Ω閘極奈米線的一個結構，它被歸類於非揮發性記憶體（NVM）。實驗結果證實，此設備具有超強的記憶特性，它的p型通道及Ω閘極結構提供了一個大的記憶窗口並且具有高的寫入/抹除效率。在104次的寫抹測試中，記憶窗口仍可維持3.5的水準。且經過85。C模擬10年後的保存能力測試，記憶體內儲存的電子數量仍有其初始值的53％。
此外，本實驗也提出了新一代無接面非揮發性記憶建立於體雙電晶體結構上。它可以被寫入，但抹除仍然是一個挑戰。令人驚訝的是，此元件具有良好的保存電子能力，具有可被應用於一次性寫入功能元件的潛力。
在未來，這些多晶矽場效非揮發性記憶體具有很大的潛力可被應用於功能面板系統，液晶顯示器和3D堆疊式快閃記憶體中.

This study proposed the n-channel and p-channel twin poly-Si fin field-effect transistor (FinFET) nonvolatile memory (NVM) with a structure that is composed of Ω-gate nanowires (NWs). Experimental results show that the NW device has superior memory characteristics because its p-channel Ω-gate structure provides a large memory window and high program/erase efficiency. With respect to endurance and retention, the memory window can be maintained at 3.5 V after 104 program and erase cycles, and after ten years, the charge is 53 % of its initial value.
Further, a new generation study of junctionless NVM was studied in this work. The memory is also based on twin structure. It can be programmed but erasing is still a challenge. Surprisingly, the device exhibits a good retention characteristic and have a great potential been used as one time programmable device.
In the future, these twin poly-Si FinFET NVM devices have a great potential to be used in multilayer Si ICs in fully functional system-on-panel, active matrix liquid crystal display and 3D stacked flash memory applications.

Contents
Contents v
Figure Captions vii

Chapter 1 vii
Chapter 2 vii
Chapter 3 viii
Chapter 4 ix

Introduction 1

1.1 Introduction to Nonvolatile Memory 1
1.1.1 The classification of storage device 2
1.2 Motivation 3
1.2.1 Thesis Organization 4

Chapter 2 9
Basic Mechanisms and Reliability of Nonvolatile Memory 9

2.1 Introduction 9
2.2 Basic Mechanisms 9
2.2.1 Fowler-Nordheim (FN) Tunneling 10
2.2.2 Direct Tunneling 11
2.2.3 Trap Assisted Tunneling 11
2.2.4 Channel Hot-Electron Injection (CHEI) 11
2.2.5 Band-to-Band Tunneling induced Hot Electron 13
2.2.6 Fowler-Nordheim (FN) Tunneling erase 14
2.3 Reliability 14
2.3.1 Endurance 14
2.3.2 Retention 15
2.3.3 Disturbs 15

Chapter 3 26
Characteristic of twin-TFT EEPROM withΩ-gate nanowire structure 26

3.1 Device structure and frabrication 26
3.2 Results and Discussion 30
Chapter 4 41
Experiment II: Characteristic of junctionless twin-TFT EEPROM
with O/N layer 41

4.1 Introduction of junctionless 41
4.2 Experimental Procedures 42
4.3 Results and discussion 43
4.3.1One time programmable device 43

Chapter 5 Conclusions and further study 53

Reference 55

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