多重相位鎖延遲迴路 (MP-DLL) 是目前常應用來產生倍頻時脈，以及在雙倍資料率同步動態隨機存取記憶體 (DDR SDRAM) 控制器中用於實現所需的固定時序延遲，以進行去時鐘偏移功能。傳統上，多重相位鎖延遲迴路的可調式延遲線 (Tunable Delay Line) 在相同的控制碼下會遭受因為製程變異引起的延遲時間不一致問題。
本篇論文開發了一種名為“檢查並平衡 (CAB) ”的校準方法，用於修正MP-DLL電路中每個延遲線之間的延遲不匹配問題，從而在合理的額外面積及功耗成本下為DDR SDRAM控制器提供更加穩健和準確的固定延遲量。我們使用90nm CMOS 製程 (供電電壓為 1.0-V) 和1.6GHz參考輸入頻率下實現我們的設計，在相同的MP-DLL電路中，通過CAB校準方法校正後，不同延遲線之間的最大峰對峰 (P2P) 延遲誤差從 51.32皮秒降低到6.76皮秒，與未加入CAB校準方法的基礎版本MP-DLL 設計相比，造成的額外面積及功耗成本分別為0.0045mm²和0.55mW。

Multi-Phase Delay Lock Loop (MP-DLL) is a common technique used in clock multipliers for clock multiplying and in DDR Memory controllers for achieving the required fixed timing delay for de-skew functionality. Traditionally, the Tunable Delay Line (TDL) that comprises the MP-DLL suffers from the delay period mismatch under the same control code, primarily caused by process variation.
In this work, a feature called Check and Balance Scheme (CAB) – is developed to fix the delay mismatch among each delay stage thereby providing a more robust and accurate fixed timing delay for Double-Date-Rate (DDR) memory controller with a reasonable amount of area overhead. In the same MP-DLL circuit, after calibration using the CAB method, the maximum peak-to-peak (P2P) delay error between different delay lines decreased from 51.32 ps to 6.76 ps. Compared to the baseline version of the MP-DLL design without the CAB calibration method, the additional area and power consumption costs incurred were 0.0045 mm² and 0.55 mW, respectively.

Abstract……………………………………………………………………………………………………………………………………………………i
摘要………………………………………………………………………………………………………………………………………………………………ii
誌謝……………………………………………………………………………………………………………………………………………………………iii
Content……………………………………………………………………………………………………………………………………………………iv
List of Figures………………………………………………………………………………………………………………………………vi
List of Tables…………………………………………………………………………………………………………………………………ix
Chapter 1 Introduction………………………………………………………………………………………………………………1
1.1 Background……………………………………………………………………………………………………………………………………1
1.2 Previous Works…………………………………………………………………………………………………………………………3
1.2.1 Comparing and Averaging Method…………………………………………………………………………3
1.2.2 Converting Quadrature Phase to Duty Cycle Method…………………………4
1.3 Objective of This Work……………………………………………………………………………………………………6
1.4 Thesis Organization……………………………………………………………………………………………………………7
Chapter 2 Preliminaries……………………………………………………………………………………………………………8
2.1 Architecture of a Primitive Multi-Phase DLL……………………………………………8
2.2 TDLs Delay Mismatch……………………………………………………………………………………………………………9
2.3 P2P Delay Mismatch……………………………………………………………………………………………………………10
Chapter 3 Proposed Check and Balance Scheme……………………………………………………11
3.1 Specification of our baseline MP-DLL Design…………………………………………11
3.1.1 Continuous TDL Pulse Distortion Issues…………………………………………………13
3.1.2 Enhancing Cell-based PD for Higher Frequency Support……………15
3.2 Overall Check and Balance Scheme………………………………………………………………………17
3.2.1 Phase Selection Circuit (PSC)…………………………………………………………………………18
3.2.2 Phase Error (PE) Monitor………………………………………………………………………………………22
3.3 Operation of Check and Balance Scheme…………………………………………………………23
3.3.1 Calibration Procedure in a Check Mode……………………………………………………23
3.3.2 Calibration Procedure in a Balance Mode………………………………………………24
3.3.3 Calibration Procedure in a Re-locking Mode………………………………………27
3.4 Potential Fault Scenarios in Delay Stage…………………………………………………28
Chapter 4 Experimental Results………………………………………………………………………………………30
4.1 Layout of Our Entire MP-DLL with CAB Scheme…………………………………………30
4.2 Post-Layout Simulation Results……………………………………………………………………………31
4.3 Potential Hard Errors Recovery Ability………………………………………………………35
4.4 Replacing with Sense Amplifier-Based PD……………………………………………………36
4.5 Performance Summary…………………………………………………………………………………………………………39
4.5.1 Supplemental Information of Custom Circuits in Each Comparative Work……………………………………………………………………………………………………………………………………………………………42
Chapter 5 Conclusion…………………………………………………………………………………………………………………46
References……………………………………………………………………………………………………………………………………………47

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