隨著半導體技術的突飛猛進，元件的尺寸微縮已趨近物理的極限。然而市場對於更高效能、高密度及低功耗的產品需求並沒有下降，因此驅使元件朝摩爾定律之外的三維堆疊發展，而要將不同的元件垂直整合，勢必會面臨許多製程上的問題，像是前後段元件製程是否相容，以及後段製程的熱預算限制，都是實現三維堆疊前需要克服的困難。
基於上述所提及之問題，本篇論文研究提出利用低溫綠光雷射結晶技術形成的複晶矽製作鰭式電晶體及鐵電記憶體，符合後段製程的低熱預算需求，並且能夠實現單晶片垂直整合，以達到記憶體內運算的能力，這將大幅降低運算元件與記憶體之間傳輸資料所需消耗的時間及能量，突破馮‧紐曼架構的極限。另外，在閘極氧化層部分，我們使用多層堆疊之氧化鉿/氧化鋯結構，相較於傳統氧化鉿鋯，此結構具有更大的介電常數，以及更薄的等效氧化層厚度，使電晶體能夠產生更大的電流。多層堆疊之氧化鉿/氧化鋯應用於鐵電記憶體，亦能產生更大的記憶窗口，並且擁有更低的缺陷密度，以達到更好的可靠度。
本篇研究將分成兩個部分，分別是作為邏輯元件的鰭式電晶體以及記憶元件的鐵電記憶體。
第一部分為綠光雷射複晶矽鰭式電晶體。如上述所說，製作於上層的元件需盡可能降低熱預算，而由於直接沉積單晶矽及複晶矽的溫度皆過高，不符合後段製程，因此我們首先沉積150奈米之非晶矽，接著使用低溫綠光雷射結晶形成複晶矽通道，再利用化學機械研磨將通道厚度減至40奈米，同時降低因雷射掃描而增加的表面粗糙度。接著，使用原子層沉積技術沉積5奈米之多層堆疊氧化鉿/氧化鋯作為閘極氧化層，並利用物理氣相沉積氮化鈦做為金屬閘極。在定義閘極區域並摻雜磷離子後，最終利用快速熱退火活化摻雜離子及鐵電層的結晶。我們所製作的鰭式電晶體擁有2.7 × 107的Ion/Ioff比值，平均次臨界擺幅達到80.2 mV/dec，DIBL亦控制在13.7 mV/V。除了優秀的電性表現，多層堆疊氧化鉿/氧化鋯之元件表現出比傳統氧化鉿鋯元件大1.9倍的飽和電流，證明此結構擁有更高的介電常數。因此，我們使用此結構另外製作p型元件並探討CMOS反相器之特性，得到筆直的電壓轉換特性曲線與155.9 V/V的最大電壓增益。
第二部分為複晶矽鰭式鐵電記憶體。此元件結構與上述之電晶體僅在閘極氧化層有不同厚度，其餘皆相同。在記憶體的鐵電層部分，我們沉積了10奈米多層堆疊氧化鉿/氧化鋯，較厚的鐵電層有助於生成較大的極化量，以提升記憶窗口的大小。我們所製作的鐵電記憶體擁有100奈秒的高操作速度，利用±5 V, 100奈秒的脈衝進行寫入/抹除操作，可得到1.93 V的記憶窗口。另外，我們對元件的可靠度進行量測，鐵電記憶體存取的資料在室溫環境下經過104秒後仍保持相當穩定，展現出良好的儲存資料能力。耐用度方面，傳統氧化鉿鋯之元件在經歷104次操作後即崩潰，而多層堆疊氧化鉿/氧化鋯之元件在經歷106次的操作後，仍能維持0.66 V之記憶窗口，證明其擁有更好的耐用度。
此論文利用低溫綠光雷射結晶之複晶矽製作電晶體與鐵電記憶體，兩者皆表現出極佳的特性，其符合後段製程之特性加上相容於CMOS製程，對於未來應用於垂直整合有著巨大的潛力。

With the advancement of semiconductor technology, device scaling has approached its physical limits. However, the market demand for products with higher efficiency, higher density, and lower power consumption has not diminished. Hence, the progression towards three-dimensional (3D) stacking has become inevitable. To integrate different components vertically will unavoidably face numerous process challenges, including assessing the compatibility of the front-end-of-line (FEOL) and back-end-of-line (BEOL) processes, as well as overcoming the thermal budget restrictions of the BEOL process. These will be the difficulties that need to be overcome to realize 3D stacking.
Based on the aforementioned issues, in this study, we propose low-temperature green laser crystallized poly-Si to fabricate fin field-effect transistors (FinFETs) and ferroelectric memories. These devices are compatible with monolithic integration, which can achieve in-memory computing to significantly reduce the time and energy consumption for data transfer between computing components and memories. For gate oxide, we utilize superlattice HfO2/ZrO2. Compared to traditional HZO, this structure exhibits a higher permittivity and thinner equivalent oxide thickness, enabling transistors to generate higher current. For memory, superlattice HfO2/ZrO2 yields a larger memory window and lower defect density, which can improve reliability characteristics.
This research will be divided into two parts, focusing on fin field-effect transistors (FinFETs) for logic applications in the first part, and on ferroelectric memory in the second part.
The first part focuses on green laser crystallized poly-Si FinFET. As mentioned above, components fabricated at the upper layer must minimize the thermal budget as much as possible. Due to the high temperature required for direct deposition of monocrystalline silicon or poly-Si, which is not BEOL-compatible, we first deposited 150 nm of amorphous silicon and then crystallized it into poly-Si with green laser. The thickness was then reduced to 40 nm using chemical mechanical polishing (CMP) while mitigating the surface roughness caused by laser. Subsequently, a 5-nm superlattice HfO2/ZrO2 was deposited by atomic layer deposition as gate oxide, followed by TiN deposition by physical vapor deposition as gate metal. After defining the gate region and doping ions, rapid thermal annealing was employed to activate dopants and crystallize the ferroelectric layer. The fabricated devices exhibited an Ion/Ioff ratio of 2.7 × 107, an average subthreshold swing of 80.2 mV/dec, and a DIBL of 13.7 mV/V. The devices with superlattice HfO2/ZrO2 exhibited a saturation current 1.9 times higher than those with conventional HZO, proving that this structure possesses a higher k-value. Therefore, we utilized this structure to fabricate the p-type transistors and investigated the characteristics of CMOS inverter, achieving an excellent voltage transfer characteristic and a voltage gain of 155.9 V/V.
The second part focuses on poly-Si ferroelectric memory. The only difference between ferroelectric memory and the aforementioned transistor device is the thickness of the oxide layer. For ferroelectric memory, we deposited a thicker 10-nm of superlattice HfO2/ZrO2, which contributes to a larger polarization to enhance memory window. The ferroelectric memory exhibited a high operation speed of 100 ns. The device exhibited a maximum memory window of 1.93 V using pulses of ± 5 V, 100 ns for program/erase operations. We also conducted reliability tests, the device demonstrated stable states after 104 s at room temperature, indicating its excellent data retention capability. In terms of endurance, conventional HZO device failed after 104 cycles, whereas superlattice HfO2/ZrO2 device maintained a memory window of 0.66 V after 106 cycles, proving its superior endurance characteristic.
In this study, we utilize green laser crystallized poly-Si to fabricate transistors and ferroelectric memories, both exhibited excellent performance. With the compatibility with both the BEOL process and CMOS process, they have significant potential for future 3D integration applications.

摘要 i
Abstract iii
誌謝 vi
目錄 vii
圖目錄 x
表目錄 xii
第一章 1
緒論 1
1.1 元件的微縮與三維堆疊 (Device Scaling and 3D Stacking) 1
1.2 低溫綠光雷射結晶技術 (Low Temperature Green Laser Crystallization) 4
1.3 二氧化鉿基材料之鐵電特性 (Ferroelectricity of HfO2-based Material) 6
1.4 超晶格二氧化鉿/二氧化鋯 (Superlattice HfO2/ZrO2) 9
1.5 鐵電記憶體 (Ferroelectric Field-effect Transistor Memory) 11
第二章 13
機制探討 13
2.1 鐵電層之厚度 (Thickness of Ferroelectricity Film) 13
2.2 電晶體重要參數 15
2.2.1 次臨界擺幅 (Subthreshold Swing) 15
2.2.2 汲極引發能障降低 (Drain Induced Barrier Lowering) 16
2.2.3 反相器操作機制 (Operating Mechanism of Inverter) 17
2.3 鐵電記憶體機制 (Mechanism of FeFET) 19
2.3.1 電荷捕捉效應 (Charge Trapping Effect) 19
2.3.2 介面層 (Interfacial Layer) 21
2.3.3 讀取造成之影響 (Impact of Read Operation) 23
第三章 25
綠光雷射複晶矽超晶格氧化鉿/氧化鋯鰭式電晶體 25
3.1 實驗動機 (Motivation) 25
3.2 製程步驟 (Device Fabrication) 26
3.3 穿透式電子顯微鏡與能量散射x射線譜分析 (TEM and EDS Analysis) 30
3.4 電特性分析 (Electrical Characteristics Analysis) 32
3.4.1 電晶體電特性分析 (FinFET Electrical Characteristics Analysis) 32
3.4.2 反相器電特性分析 (Inverter Electrical Characteristics Analysis) 36
第四章 39
綠光雷射複晶矽超晶格氧化鉿/氧化鋯鰭式鐵電記憶體 39
4.1 實驗動機 (Motivation) 39
4.2 製程步驟 (Device Fabrication) 41
4.3 穿透式電子顯微鏡與能量散射X射線譜分析 (TEM and EDS Analysis) 43
4.4 記憶窗口與脈衝電壓分析 (Memory Window and Pulse Voltage Analysis) 45
4.5 可靠度分析 (Reliability Analysis) 51
第五章 54
結論與未來展望 54
5.1 結論 (Conclusion) 54
5.2 未來展望 (Future Work) 55
參考文獻 56

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