本篇論文主要探討了在使用以矽作為通道材料的(100)晶面為主的奈米片互補式場效電晶體(Nanosheet CFET, NSCFET)，以及針對電子在(100)晶面為主導的NMOS Nanosheet與(110)晶面為主導的PMOS FinFET 所形成的之互補式場效電晶體(N-Nanosheet P-FinFET CFET, NNSPFFCFET)，並且使用了埋入式電源軌(Burrier Power Rail, BPR)以增加元件的接線空間，並減小元件體積，而在研究中我們將探討這種結構對於不同結構變化對於兩種CFET結構的影響，其中包含通道寬度(Channel width ,Wch)與奈米片厚度(Channel thickness, Tch)，以及混和晶面結構下的PMOS通道寬度與PMOS鰭片高度(Fin hight, FH )。
根據模擬結果所示NSCFET在次臨界斜率以及DIBL中具有優勢，但由於NSCFET以(100)晶面為主，使其PMOS的Gm較低以及ID-VD不對稱，而NNSPFF CFET則是顯示出較高的Gm以及對稱的ID-VD，但由於FinFET結構的短通道效應較為明顯，使PMOS的SS以及DIBL較差。
接下來我們模擬了這兩種CFET架構的邏輯電路性能，以及其SRAM的雜訊邊界以及反向器之VTC並進行比較，這兩種結構展現出各自的優缺點。
總而言之，本研究比較了兩種CFET結構，並分析了其電性對結構的相依性，並可以有效延續摩爾定律至一奈米節點。

This paper primarily investigates nanosheet complementary field-effect transistors (Nanosheet CFET, NSCFET) using silicon as the channel material with a focus on the (100) crystal plane. It also explores complementary field-effect transistors formed with NMOS nanosheets dominated by the (100) crystal plane and PMOS FinFETs dominated by the (110) crystal plane (N-Nanosheet P-FinFET CFET, NNSPFFCFET). Additionally, buried power rails (BPR) are utilized to increase routing space and reduce device area. This study examines the impact of various structural changes on these two CFET structures, including channel width (Wch) and nanosheet thickness (Tch), as well as the PMOS channel width and PMOS fin height (FH) in mixed crystal plane structures.
According to the simulation results, NSCFET has advantages in subthreshold slope (SS) and drain-induced barrier lowering (DIBL). However, because NSCFET is primarily based on the (100) crystal plane, it results in lower PMOS transconductance (Gm) and asymmetric ID-VD characteristics. On the other hand, NNSPFF CFET shows higher Gm and symmetric ID-VD characteristics, but due to the significant short-channel effects of the FinFET structure, it has poorer SS and DIBL for the PMOS.

Next, we simulated the logic circuit performance of these two CFET architectures, as well as the noise margin of their SRAM and the VTC of their inverters, making comparisons between them. Each structure exhibits its own strengths and weaknesses.
In summary, this study compares the two CFET structures, analyzes the dependence of their electrical characteristics on structural variations, and demonstrates the potential to effectively extend Moore's Law to the N1 node.

摘要 i
Abstract ii
致謝 iv
目錄 v
圖目錄 vii
表目錄 xi
第一章 1
緒論 1
1.1 摩爾定律的演進 (More Moore) 1
1.2 互補式場效電晶體 (Complementary FET, CFET) 5
1.3 埋入式電源軌 (Burrier Power Rail) 10
1.4 不同晶向對於矽材料遷移率的影響(Surface Orientation Effect) 13
1.5 研究動機 (Motivation) 18
1.6 論文組織 (Thesis Organization) 21
第二章 23
機制探討 23
2.1 金屬氧化物半導體場效電晶體(Metal Oxide Semiconductor Field Effect Transistor, MOSFET) 23
2.2 MOSFET關鍵參數 26
2.2.1 臨界電壓(Threshold Voltage, VTH) 26
2.2.2 次臨界斜率(Subthreshold Swing ,SS) 26
2.2.3 汲極引發位能障降低(Drain Induced Barrier Lowering ,DIBL) 28
2.2.4 轉導(Transconductance ,Gm) 29
2.3 互補式金屬氧化物半導體(Complementary Metal Oxide Semiconductor ,CMOS) 30
第三章 33
TCAD模擬互補式場效電晶體 33
3.1 TCAD簡介 33
3.2 元件結構 34
3.3 通道寬度與厚度調變對於元件性能的影響 37
3.4 元件特性分析 49
第四章 52
邏輯電路性能分析 52
4.1 NSCFET之邏輯電路性能分析 54
4.2 NNSPFFCFET之邏輯電路性能分析 61
4.3 總結 69
第五章 73
5.1 結論 73
5.2 未來展望 75
參考文獻 76

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第二章
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第五章
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