帳號:guest(216.73.216.146)          離開系統
字體大小: 字級放大   字級縮小   預設字形  

詳目顯示

以作者查詢圖書館館藏以作者查詢臺灣博碩士論文系統以作者查詢全國書目
作者(中文):許芳瑜
作者(外文):Hsu, Fang-Yu
論文名稱(中文):針對雙面繞線且基於邊界框的網表規劃方法
論文名稱(外文):A Bounding Box-based Net Partitioning Method for Double-sided Routing
指導教授(中文):麥偉基
指導教授(外文):Mak, Wai-Kei
口試委員(中文):王廷基
陳勝雄
口試委員(外文):Wang, Ting-Chi
Chen, Sheng-Hsiung
學位類別:碩士
校院名稱:國立清華大學
系所名稱:半導體研究學院
學號:110501701
出版年(民國):113
畢業學年度:112
語文別:英文
論文頁數:39
中文關鍵詞:背面供電網路雙面訊號繞線
外文關鍵詞:back-side power delivery networkdouble-sided signal routing
相關次數:
  • 推薦推薦:0
  • 點閱點閱:822
  • 評分評分:*****
  • 下載下載:0
  • 收藏收藏:0
傳統的晶片內電源分配網絡是建構於正面金屬層上。為了在尺寸微縮的考量下改進電源分布網路,背面電源分布網路的概念被提出,該技術將電源分布網路從正面金屬層中分離出來,並利用晶片的背面金屬層建構主要的電源分布網路。為了充分利用在構建電源分布網路後剩餘的背面繞線資源,文獻[1]介紹了一種能夠將一組信號網分配到兩側的網表規劃流程。然而文獻[1]沒有考量分別分配給正面和背面的引腳的邊界框之間的重疊區域(稱為重疊邊界框),可能導致線長增加。為了減輕這個缺點,我們提出了一種基於邊界框的網表規劃方法來改善在文獻[1]中描述的方法。主要目標是減少分別分配正面和背面的兩個引腳邊界框之間的重疊區域,同時試著將盡可能多的關鍵網引腳分配到背面。此外,我們利用一種電源分布網路感知資源方法來根據電源分布網路調整橋接單元資源以及繞線資源以進行準確資源估計。

我們將我們的網表規劃方法與[1]中提出的方法進行比較,並在商業工具中執行佈局和佈線。實驗結果表明,平均線長減少了2%,關鍵網路的平均時序分數減少了6.4%。此外,我們在每個測試案例中產生了零個設計規則檢查。與我們基於工具的網表規劃方法相比。我們高效的佈線分析技術不僅將平均線長縮短了 7.4%,而且還實現了基線 38 倍以上的加速。
A conventional on-die power delivery network (PDN) is constructed using the front-side metal stacks. To improve the PDN efficiency under the consideration of scaling trends, back-side PDN has been proposed. This technique separates the PDN from the front-side metal stacks and utilizes primarily the back-side metal stacks for the PDN. To well utilize the remaining routing resources on the back side after constructing the PDN, [1] introduced a netlist planning flow capable of distributing a set of signal nets to both sides. However, [1] does not consider the overlapping regions between bounding boxes of pins assigned to the front side and back side, respectively (referred to as overlapping bounding boxes), potentially leading to increased wirelength. To mitigate this drawback, we propose a bounding box-based netlist planning approach to improve the quality of [1]. The primary goal is to reduce the size of overlapping bounding boxes, and try to assign as many pins of the critical nets as possible to the back side. Additionally, we introduce a PG-aware capacity calculation to adjust the bridging cell capacities and the routing capacities following the PDN for accurate resource estimation.

We compare our netlist planning approach with that proposed in [1] and perform placement and routing in the commercial tool. Experimental results show that the average wirelength is less by 2%, and the average timing score for the critical nets is reduced by 6.4%. Moreover, we achieve zero DRC violations in each testcase. Compared to a tool-based netlist planning method that we implemented, our efficient routing analysis techniques not only reduce the average wirelength by 7.4% but also achieve over a 38 times speedup of the baseline.
1 Introduction 1
1.1 Motivation 1
1.2 Contribution 4
1.3 Organization 6
2 Preliminaries 7
2.1 Problem Formulation 7
2.2 Global Routing 8
2.3 RUDY 9
3 Proposed Approach 11
3.1 PG-aware Capacity Calculation 13
3.2 Initial Partitioning of Critical nets 14
3.3 BBOX-based Partitioning 18
3.3.1 Overview 18
3.3.2 Enumerate the Partitioning Solutions 19
3.3.3 Partitioning Cost Function 21
3.3.4 Free Pin Allocation 24
3.3.5 Final Partitioning Solution 24
3.4 Connection Point Assignment 26
4 Experimental Results 27
4.1 Experimental Environment and Benchmarks 27
4.2 Results 28
4.2.1 Comparison of different capacity estimation methods 29
4.2.2 Comparison of three different partitioning methods 29
5 Conclusion 37
Bibliography 39
[1] T.-C. Lin, F.-Y. Hsu, W.-K. Mak, and T.-C. Wang, “An effective netlist planning approach
for double-sided signal routing,” Proceedings of 2024 Asia and South Pacific Design Automation Conference, 2024.
[2] E. B. Ryckaert, “An integrated circuit chip with power delivery network on the backside of
the chip,” in European Patent EP3324436A1, 2017.
[3] W. H. et al, “Intel powervia technology: Backside power delivery for high density and
high-performance computing,” in IEEE Symposium on VLSI Technology and Circuits (VLSI
Technology and Circuits), pp. 1–2, 2023.
[4] G. Sisto, R. Preston, R. Chen, G. Mirabelli, A. Farokhnejad, Y. Zhou, I. Ciofi, A. Jourdain,
A. Veloso, M. Stucchi, O. Zografos, P. Weckx, G. Hellings, and J. Ryckaert, “Block-level
evaluation and optimization of backside pdn for high-performance computing at the a14
node,” in IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), pp. 1–2, 2023.
[5] E. Beyne, A. Jourdain, and G. Beyer, “Nano-through silicon vias (ntsv) for backside power
delivery networks (bspdn),” in IEEE Symposium on VLSI Technology and Circuits (VLSI
Technology and Circuits), pp. 1–2, 2023.
[6] J. Ryckaert, A. Gupta, A. Jourdain, B. Chava, G. Van der Plas, D. Verkest, and E. Beyne,
“Extending the roadmap beyond 3nm through system scaling boosters: A case study on
buried power rail and backside power delivery,” in 2019 Electron Devices Technology and
Manufacturing Conference (EDTM), pp. 50–52, 2019.
[7] S.-H. Chen, J. C. J. Kao, K.-N. Yang, and J. Liu, “System and method for back side signal
routing,” in U.S. Patent 11423204, 2022.
[8] Y.-J. Chang, Y.-T. Lee, J.-R. Gao, P.-C. Wu, and T.-C. Wang, “Nthu-route 2.0: A robust
global router for modern designs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 12, pp. 1931–1944, 2010.
[9] P. Spindler and F. M. Johannes, “Fast and accurate routing demand estimation for efficient
routability-driven placement,” in 2007 Design, Automation Test in Europe Conference Exhibition, pp. 1–6, 2007.
 
 
 
 
第一頁 上一頁 下一頁 最後一頁 top
* *