本次設計以CMOS影像感測器(CMOS Image Sensor, CIS)後端之類比數位轉換器(Analog to Digital Convertor, ADC)為應用目標，設計一個具有12位元有效位數(Effective Number of Bits, ENOB)、一百千赫茲(100 kHz)頻寬、取樣頻率為一千萬赫茲(10 MHz)之類比數位轉換器電路，同時功率消耗控制在微瓦(micro Watt)等級。
本論文在ADC架構上採用的是連續漸進式類比數位轉換器(Successive Approximation ADC, SAR ADC)，然而多位元數之連續漸進式轉換器最主要的缺點就是電容面積容易過大，因此本論文利用了 passive noise shaping的方式在10位元SAR ADC的結構上實施雜訊重塑，有效提升ADC的ENOB到12 bits，不只更能降低功耗也更省面積。相較主動雜訊調變，被動雜訊調變之優勢為其架構簡單，且主要使用被動元件，不須額外偏壓電路供放大器使用。此外，ADC內部雜訊會造成比較錯誤，因此本論文加入數位錯誤校正電路，能有辦法用一個演算法修正數位輸出的位元。
本論文電路是在 TSMC 0.18 μm 1P6M CMOS製程下實現，晶片總面積包含TSMC的 ESD I/O pad為0.88 mm2，此類比數位轉換器的供應電壓為1.8 V、取樣頻率10 MHz。當訊號背景為輸入 129.39 kHz 的正弦波時，訊號對雜訊及失真比（SNDR）以及有效位元數（ENOB）的模擬結果分別是 86 dB 以及 14-bit，而平均功耗的結果為962 μW。在量測結果中，整體晶片(包括驅動電路)共消耗1723 μW。在頻寬為312.5 kHz情況下有效位數為10.62位元，若縮減頻寬至156.25 kHz，則有效位數可達12.1位元。

The design focuses on the analog-to-digital converter at the backend of the CMOS Image Sensor (CIS) as its application target. It aims to design an ADC circuit with 12-bit Effective Number of Bits (ENOB), 100 kHz bandwidth, and a sampling frequency of 10 MHz, while keeping the power consumption at micro Watt level. The paper adopts a Successive Approximation ADC (SAR ADC) architecture for the ADC design. However, the main drawback of the multi-bit successive approximation converters is the tendency for the capacitor area being too large. Therefore, this paper utilizes passive noise shaping to implement noise shaping in the structure of the 10-bit SAR ADC, effectively increasing the ADC's ENOB to 12 bits. This not only reduces power consumption but also saves area. Compared to active noise modulation, passive noise modulation has the advantages of the simpler structure and primarily using passive components without additional bias circuits for amplifiers. Furthermore, since internal noise in ADCs can cause quantization errors, this paper adds a digital error correction circuit, which can correct the digital output using an algorithm. The circuit is implemented in the TSMC 0.18 μm 1P6M CMOS process, with the total chip area including TSMC's ESD I/O pad being 0.88 mm2. The supply voltage for the ADC is 1.8 V, and the sampling frequency is 10 MHz. Simulation results with the input signal of a 129.39 kHz sine wave show a Signal-to-Noise and Distortion Ratio (SNDR) of 86 dB and an ENOB of 14 bits. The average power consumption is 962 μW. In the measurement results, the overall chip (including driver circuit) consumes a total of 1723 μW. At a bandwidth of 312.5 kHz, the effective number of bits is 10.62 bits. Reducing the bandwidth to 156.25 kHz increases the effective number of bits to 12.1 bits.

致謝 i
摘要 ii
Abstract iii
圖目錄 vii
表目錄 ix
第一章 緒論 1
1.1 研究背景 1
1.2 研究動機 2
1.3 論文章節架構 3
第二章 連續漸進式類比數位轉換器 4
2.1 SAR ADC介紹 4
2.2 連續漸進式切換機制 6
2.2.1 傳統切換與單調(Monotonic)切換 6
2.2.2 C-DAC電荷注入 8
2.3 轉換器規格介紹 9
2.4 過取樣與雜訊調變 10
2.5 ADC參數介紹 11
第三章 電路架構 13
3.1 過取樣類比數位轉換器架構 13
3.2 靴帶式開關取樣電路 14
3.3 被動雜訊調變 15
3.4 電容陣列 16
3.5 動態比較器電路 17
3.6 連續漸進式轉換邏輯 18
3.7 數位錯誤校正電路 20
第四章 模擬與佈局 22
4.1 設計流程 22
4.2 模擬方法與環境介紹 24
4.3 Pre simulation 25
4.3.1 採樣電路與比較器 25
4.3.2 線性度表現 27
4.4 佈局介紹 32
4.4.1 比較器 32
4.4.2 電容陣列 32
4.4.3 整體電路佈局 33
4.5 Post simulation 34
4.6 模擬結果與文獻比較 36
第五章 量測環境設計與結果 38
5.1 印刷電路板(Printed Circuit Board, PCB)設計 38
5.1.1 PCB Schematic 38
5.1.2 PCB Layout 39
5.2 量測設定 41
5.3 量測結果與討論 44
5.3.1 模擬與量測結果比較 44
5.3.2 功率消耗 46
5.3.3 不同輸入頻率比較 47
5.3.4 驗證不同訊號產生器所產生雜訊差異 49
第六章 總結與研究建議 51
6.1 總結 51
6.2 後續研究建議 52
6.2.1 電路功耗與面積取捨 52
6.2.2 靜態功率消耗 54
6.2.3 C-DAC Mismatch對電路之影響 55
6.2.4 數位類比之間的雜訊隔絕 57
6.2.5 二階雜訊整形 58
參考文獻 59
附錄 量測資料 62

[1] Wu, J.-T., Analog-Digital Interfaces. Data-Conversion Integrated Circuits, April 29, 2020.
[2] Lin, C. Y., Lin, Y. Z., Tsai, C. H., & Lu, C. H. (2021, February). 27.5 an 80MHz-BW 640MS/s time-interleaved passive noise-shaping SAR ADC in 22nm FDSOI process. In 2021 IEEE International Solid-State Circuits Conference (ISSCC) (Vol. 64, pp. 378-380). IEEE.
[3] Jie, L., Zheng, B., & Flynn, M. P. (2019, February). 20.3 A 50MHz-bandwidth 70.4 dB-SNDR calibration-free time-interleaved 4 th-order noise-shaping SAR ADC. In 2019 IEEE International Solid-State Circuits Conference-(ISSCC) (pp. 332-334). IEEE.
[4] Shu, Y.-S., L.-T. Kuo, and Tien-Yu Lo, An Oversampling SAR ADC With DAC Mismatch Error Shaping Achieving 105 dB SFDR and 101 dB SNDR Over 1 kHz BW in 55 nm CMOS. IEEE Journal of Solid-State Circuits, 2016. 51(12): pp. 2928-2940.
[5] Lin, Y. Z., Lin, C. Y., Tsou, S. C., Tsai, C. H., & Lu, C. H. (2019, February). 20.2 A 40MHz-BW 320MS/s passive noise-shaping SAR ADC with passive signal-residue summation in 14nm FinFET. In 2019 IEEE International Solid-State Circuits Conference-(ISSCC) (pp. 330-332). IEEE.
[6] Kester, W. (2005, December). Which ADC architecture is right for your application. In EDA Tech Forum (Vol. 2, No. 4, pp. 22-25).
[7] Liu, C. C., Chang, S. J., Huang, G. Y., & Lin, Y. Z. (2010). A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure. IEEE Journal of Solid-State Circuits, 45(4), 731-740.
[8] Fredenburg, J. A., & Flynn, M. P. (2012). A 90MS/s 11MHz bandwidth 62dB SNDR noise-shaping SAR ADC. IEEE Journal of Solid-State Circuits, 47(12), 2898-2904.
[9] Razavi, B., The Bootstrapped Switch [A Circuit for All Seasons], in IEEE Solid-State Circuits Magazine. Summer 2015. pp. 12-15.
[10] Gandara, M., Guo, W., Tang, X., Chen, L., Yoon, Y., & Sun, N. (2017, April). A pipelined SAR ADC reusing the comparator as residue amplifier. In 2017 IEEE Custom Integrated Circuits Conference (CICC) (pp. 1-4). IEEE.
[11] Liu, C. C., Chang, S. J., Huang, G. Y., Lin, Y. Z., Huang, C. M., Huang, C. H., ... & Tsai, C. C. (2010, February). A 10b 100MS/s 1.13 mW SAR ADC with binary-scaled error compensation. In 2010 IEEE International Solid-State Circuits Conference-(ISSCC) (pp. 386-387). IEEE.
[12] Li, S., Qiao, B., Gandara, M., & Sun, N. (2018, February). A 13-ENOB 2 nd-order noise-shaping SAR ADC realizing optimized NTF zeros using an error-feedback structure. In 2018 IEEE International Solid-State Circuits Conference-(ISSCC) (pp. 234-236). IEEE.
[13] Guo, W., & Sun, N. (2016, September). A 12b-ENOB 61µW noise-shaping SAR ADC with a passive integrator. In ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference (pp. 405-408). IEEE.
[14] Zhuang, H., Guo, W., Liu, J., Tang, H., Zhu, Z., Chen, L., & Sun, N. (2019). A second-order noise-shaping SAR ADC with passive integrator and tri-level voting. IEEE Journal of Solid-State Circuits, 54(6), 1636-1647.
[15] Zhu, Y., Chan, C. H., Chio, U. F., Sin, S. W., Seng-Pan, U., Martins, R. P., & Maloberti, F. (2010). A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS. IEEE Journal of Solid-state circuits, 45(6), 1111-1121.
[16] Sekimoto, R., Shikata, A., Yoshioka, K., Kuroda, T., & Ishikuro, H. (2013). A 0.5-V 5.2-fJ/conversion-step full asynchronous SAR ADC with leakage power reduction down to 650 pW by boosted self-power gating in 40-nm CMOS. IEEE Journal of Solid-State Circuits, 48(11), 2628-2636.
[17] Kim, W., Hong, H. K., Roh, Y. J., Kang, H. W., Hwang, S. I., Jo, D. S., ... & Ryu, S. T. (2016). A 0.6 V 12 b 10 MS/s low-noise asynchronous SAR-assisted time-interleaved SAR (SATI-SAR) ADC. IEEE Journal of Solid-State Circuits, 51(8), 1826-1839.