在現今的電子產品中，任何具有時序控制的電路，例如手機、相機、電腦等，都必須依賴時脈訊號來確保正確運作。因此，如何生成一個高度精確且穩定的時脈訊號成為一個重大的課題。迄今為止，大多數電子設備仍然依賴石英振盪器產生時脈訊號，這主要是因為石英振盪器提供了目前最高的頻率穩定性，然而，石英晶體作為振盪器的基本元件，有大面積、高成本、高消耗功率，以及無法與CMOS製成做整合等的缺點，因此過去幾十年來各界學者都試圖尋找能替代石英振盪器的方案，以追求更好的時脈訊號生成技術。
近年來被提出取代石英振盪的方法有MEMS振盪器、FBAR振盪器，及CMOS振盪器。但是，MEMS與FBAR的製程技術困難，無法與CMOS電路整合；而CMOS振盪器因半導體特性易受環境影響，導致其振盪頻率會因工作溫度與供應電壓的變動而改變。也因此，到目前為止石英振盪器還無法完全被取代。不過，CMOS電路在設計上可加上適當的補償方式將穩定度提高，因此我們致力於CMOS振盪器，以標準製程下實現低功率消耗、具溫度補償的時脈產生器。
因此本次研究致力於在TSMC 90nm 1P9M 標準製程下在CMOS電路設計上製作一個高效率且穩定的時脈產生器，使其振盪頻率可以不受溫度還有電壓的變異所影響。此外，透過只有一組充放電路徑可以有效地降低週期抖動(Period Jitter)，並且加入一個除頻器以達到輸出訊號為接近50%責任週期(Duty Cycle)的方波。

In today's electronic products, any circuit with timing control, such as mobile phones, cameras, computers, etc, must rely on clock signals to ensure correct operation. Therefore, how to generate a highly accurate and stable clock signal has become a significant issue. So far, most electronic devices still rely on quartz oscillators to generate clock signals. This is mainly because quartz oscillators provide the highest frequency stability currently. However, quartz crystals, as the essential components of oscillators, have large areas and high costs. Therefore, in the past few decades, scholars from all walks of life have tried to find alternatives to quartz oscillators in pursuit of better clock signal generation technology.
In recent years, MEMS oscillators, FBAR oscillators, and CMOS oscillators have been proposed to replace quartz oscillators. However, the process technology of MEMS and FBAR is complicated and cannot integrate with CMOS circuits. Due to the characteristics of semiconductors, CMOS oscillators are easily affected by the environment, causing their oscillation frequency to change due to changes in operating temperature and supply voltage. Therefore, quartz oscillators can only partially be replaced so far. However, appropriate compensation methods can be added to the design of CMOS circuits to improve stability. Therefore, we are committed to CMOS oscillators to achieve low power consumption and temperature-compensated clock generators under standard manufacturing processes.
Therefore, this research is dedicated to creating a high-efficiency and stable clock generator based on CMOS circuit design under the TSMC 90nm 1P9M standard process so that its oscillation frequency will not be affected by temperature and voltage variations. In addition, period jitter can be effectively reduced by having only one set of charge and discharge paths, and a frequency divider is added to achieve a square wave output signal close to 50% of the duty cycle.

摘要 I
ABSTRACT II
致謝 III
目錄 IV
圖目錄 VII
表目錄 XI
第一章 緒論 1
1.1 研究背景 1
1.2 研究動機 2
1.3 論文章節架構 6
第二章 CMOS振盪器 7
2.1 CMOS振盪器介紹 7
2.1.1弛張振盪器(Relaxation Oscillator) 7
2.1.2諧波振盪器(Harmonic Oscillator) 8
2.2 頻率變異來源 10
第三章 文獻回顧 14
3.1 平均電壓值回授(VOLTAGE AVERAGING FEEDBACK) 14
3.2 電阻的串並聯或並串聯組合 18
3.3 具溫度補償的弛張振盪電路 22
第四章 電路架構 23
4.1 電路架構概述 23
4.2 雜訊分析 24
4.3 子電路 26
4.3.1 平均電壓值回授(Voltage Averaging Feedback) 26
4.3.2 運算放大器(Operational Amplifier) 28
4.3.3 比較器(Comparator) 29
4.3.4 緩衝電路(Buffer) 31
4.3.5 固定轉導偏壓電路(Constant-Gm Biasing) 31
4.3.6 充放電路徑(RC Path) 34
4.3.7 Control Buffer 36
4.3.8 Delay Buffer 37
4.3.9 除頻器(Frequency Divider) 38
4.3.10 Buffer Chain 40
4.4 振盪頻率 41
第五章 模擬與佈局 42
5.1 子電路模擬結果 42
5.1.1運算放大器(Operational Amplifier) 42
5.1.2比較器(Comparator) 44
5.1.3緩衝電路(Buffer) 46
5.1.4固定轉導偏壓電路(Constant-Gm Biasing) 47
5.1.5充放電路徑(RC Path) 50
5.1.6 Control Buffer 52
5.1.7 Delay Buffer 53
5.1.8 除頻器(Frequency Divider) 54
5.2 整體電路模擬結果 55
5.2.1 振盪器波形 55
5.2.2 穩定時間 57
5.2.3 週期抖動(Period Jitter) 58
5.2.4 工作週期(Duty Cycle) 59
5.2.5 頻率受溫度的影響 60
5.2.6 頻率受供應電壓的影響 62
5.3 晶片布局 63
第六章 量測結果 66
6.1 PCB板的設計與環境架設 66
6.2 量測儀器介紹 68
6.3 量測方法 69
6.4 量測結果 70
6.4.1 振盪器輸出波形 71
6.4.2 頻率受供應電壓的影響 73
6.4.3 頻率受溫度的影響 74
6.4.4 週期抖動受溫度的影響 75
6.4.5 量測結果彙整 76
6.5問題討論 77
第七章 結論與未來研究方向 80
7.1 結論 80
7.2 後續研究建議 80
參考文獻 83
附錄 量測資料 86

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