一次性寫入記憶體在生活中的各種電子產品與系統中具有十分廣泛的應用，從缺陷單元補救電路的位置儲存，類比電路的輸入輸出微調，到優化IC生產控制上，都可見其蹤影。一次性寫入記憶體相較於傳統的電荷儲存式快閃記憶體來說，在一次性記憶的功能上具有更好的資料保存可靠度。而隨著科技的不斷發展，一次性寫入記憶體的需求也將持續地增加，以滿足不斷增長的數據儲存需求。
傳統的1T1R一次性寫入記憶體元件，因較大的電晶體尺寸與高編程電壓，難以達到高密度的陣列，並且對於周邊電路也有著較高的要求。因此本篇論文提出一超低寫入電壓之1T2R金屬熔絲一次性寫入記憶體元件，相容於16奈米鰭式場效電晶體標準CMOS邏輯製程，利用改良的金屬熔絲結構與額外的電流分流徑，並透過縮小選擇電晶體的尺寸，來實現低電壓編程與高密度記憶體陣列。此元件除了能以1.2V的低電壓進行編程，還可用1.48μm^2的單元面積來實現高密度的陣列，並具有5000倍以上的讀取窗口，在高溫下也展現了優良的資料保存可靠度。
本篇論文另提出一相容於標準CMOS邏輯製程之高密度1T1R1D金屬熔絲一次性寫入記憶體元件，利用二極體取代原本1T2R元件的電流分流徑，如此一來便可有效解決其潛行電流的問題，不須做額外的陣列分區，達到比1T2R架構更高密度之記憶體陣列。

One-time-programmable (OTP) memory finds wide-ranging applications in various electronic devices and systems, including storage of repair information for redundancy circuits, analog circuit trimming, and storage of calibration parameters for optimizing production in IC foundry. OTP memory offers better reliability at one-time storage compared to traditional charge-trap flash memory. As technology continues to advance, the rising demand for OTP memory will continue, to meet the growing data storage needs.
The conventional 1T1R OTP memory has faced challenges in reducing its size to achieve high-density arrays due to larger transistor sizes and higher program voltages, which pose higher requirements for the peripheral circuits of the array. Therefore, this paper proposes a 1T2R Metal-Fuse OTP memory featuring ultra-low program voltage and is compatible with the standard 16 nm FinFET CMOS logic process. It accomplishes low-voltage programming at 1.2V and a high-density memory array of a 1.48μm^2 bit cell area through an improved metal fuse structure, an additional current divider, and the reduction of the select transistor size. It also exhibits a read window of over 5000 times and demonstrates good reliability under high temperatures.
This paper also proposed a high-density 1T1R1D Metal-Fuse OTP memory that is compatible with the standard CMOS logic process. It utilizes a diode to replace the current divider of the original 1T2R OTP, effectively addressing the issue of sneak currents. This eliminates the need for additional array partitioning and achieves a higher density memory array compared to the 1T2R architecture.

摘要...i
致謝...iii
章節目錄...v
附圖目錄...viii
附表目錄...xi
公式目錄...xii
第一章 緒論...1
1.1 前言...1
1.2 記憶體簡介...2
1.3 論文綱要...4
第二章 一次性寫入記憶體技術回顧與物理機制...5
2.1 一次性寫入記憶體應用與技術回顧...5
2.1.1 多晶矽熔絲記憶體元件（Poly-Fuse）...6
2.1.2 金屬熔絲記憶體元件（Metal-Fuse）...6
2.1.3 反熔絲記憶體元件（Anti-Fuse）...7
2.2 1T1R金屬熔絲一次性寫入記憶體元件...9
2.3 金屬熔絲寫入之物理機制與模型...10
2.3.1 電遷移（Electromigration）...10
2.3.2 焦耳加熱與熱遷移（Joule heating & Thermomigration）...11
2.3.3 應力遷移（Stress migration）...12
2.4 小結...13
第三章 超低寫入電壓之金屬熔絲記憶體元件...27
3.1 1T2R記憶體元件結構與陣列...27
3.1.1 單元結構與熔絲結構...27
3.1.2 陣列結構...28
3.2 記憶體元件操作原理...30
3.2.1 資料寫入（Program）...30
3.2.2 資料讀取（Read）...30
3.3 記憶體元件量測分析...31
3.3.1 量測儀器與環境參數之設定...31
3.3.2 基本特性量測...31
3.3.3 可靠度分析...32
3.4 小結...34
第四章 高密度之金屬熔絲記憶體元件...53
4.1 1T1R1D記憶體元件結構與陣列...53
4.1.1 單元結構...53
4.1.2 陣列結構...54
4.2 記憶體元件操作原理...56
4.2.1 資料寫入（Program）...56
4.2.2 資料讀取（Read）...56
4.3 記憶體元件量測分析...57
4.3.1 量測儀器與環境參數之設定...57
4.3.2 基本特性量測...57
4.4 小結...59
第五章 新型金屬熔絲記憶體之特性模擬與比較...68
5.1 1T2R記憶體陣列TCAD模擬...68
5.1.1 金屬熔絲電流密度與溫度模擬分析...69
5.1.2 記憶體陣列潛行電流模擬分析...69
5.2 1T2R與1T1R1D記憶體陣列之電性模擬...70
5.3 1T1R、1T2R與1T1R1D記憶體陣列比較...71
5.4 小結...72
第六章 總結...79
6.1 結語...79
6.2 未來展望...80
參考文獻...81

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