帳號:guest(216.73.216.146)          離開系統
字體大小: 字級放大   字級縮小   預設字形  

詳目顯示

以作者查詢圖書館館藏以作者查詢臺灣博碩士論文系統以作者查詢全國書目
作者(中文):周伯宇
作者(外文):Chou, Po-Yu
論文名稱(中文):基於線長優化的自動化元件擺置參數調整
論文名稱(外文):Automated Placement Parameter Tuning for Wire Length Optimization
指導教授(中文):王廷基
指導教授(外文):Wang, Ting-Chi
口試委員(中文):麥偉基
陳宏明
口試委員(外文):Mak, Wai-Kei
Chen, Hung-Ming
學位類別:碩士
校院名稱:國立清華大學
系所名稱:資訊工程學系
學號:110062552
出版年(民國):113
畢業學年度:112
語文別:英文
論文頁數:34
中文關鍵詞:參數優化機器學習設計工具神經網路
外文關鍵詞:parameter optimizationmachine learningdesign toolneural network
相關次數:
  • 推薦推薦:1
  • 點閱點閱:0
  • 評分評分:*****
  • 下載下載:0
  • 收藏收藏:0
隨著科技的不斷進步,超大規模積體電路(VLSI)設計流程日益複雜,
並面臨縮短上市時間的壓力。在邏輯合成以及實體設計方面,為了實現性
能、功耗及面積的目標,工程師通常會花費大量時間來調整設計工具的參
數設定。設計工具提供許多可顯著影響設計品質的可調參數。然而,由於
工具評估耗時,加上每次合成運行只能使用一種可能的參數組合,手動搜
索眾多參數的最佳組合被證明是難以實現的。由於對這些參數的微小改變
可能會導致結果的品質 (QoR) 發生巨大變化,自動調整工具參數以減少成
本迫在眉睫。由於元件擺置的品質在實體設計流程中至關重要。本論文提
出一種基於機器學習的參數推薦方法,目標是優化元件擺置階段的參數。
我們透過以一個商用工具做為研究案例,以及在少數電路上,有系統地蒐
集有限的特徵,與參數組合當作訓練資料,機器學習模型能對未曾看過的
測試電路推薦良好的參數組合。實驗證實,在線長方面,比起預設的參數
設定,模型推薦的參數組合,平均能夠優化 7.6%。
With ongoing process advancements, VLSI design encounters rising intricacies in design and the urgency to accelerate time to market. In terms of logic synthesis as well as physical design, human engineers often spend a lot of time adjusting multiple settings of commercial tools to achieve PPA goals, as tools offer a multitude of customizable parameters that can have a substantial impact on the design quality. However, manual searching for the best configurations of numerous parameters has become impractical due to the time-intensive process of tool evaluation and the limitation of using only one parameter combination per synthesis run. Since small changes to these parameters can lead to large changes in the quality of results (QoR), there is an urgent need to automatically adjust tool parameters to reduce costs. The quality of placement is critical in the physical design process. This thesis proposes a parameter recommendation method based on machine learning, to optimize the parameters in the placement stage. By taking a commercial tool as a case study and systematically collecting limited features and parameter combinations on a small number of designs as training data, our machine learning-based method can recommend good parameter combinations on unseen designs. The experiments confirm that, in terms of wire length, the parameter combinations recommended by the model, compared to the default parameter settings, can achieve an average reduction of 7.6%.
Contents
1 Introduction 1
1.1 VLSI Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Previous Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Our Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.5 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Problem Formulation 8
3 Methodology 10
3.1 Work Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Netlist Topological Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4 Machine-Learning Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5 Model Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6 Scenario Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4 Experimental Results 18
4.1 Experiment Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2 Comparative Analysis of Sampling Algorithms . . . . . . . . . . . . . . . . . 19
4.3 Evaluation Metrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.4 Parameter Tuning Performance . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.5 Post-routing Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
ii
4.6 Runtime and Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5 Conclusion 31
5.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
References 33
[1] J. Knechtel, J. Gopinath, M. Ashraf, J. Bhandari, O. Sinanoglu, and R. Karri, “Benchmarking security closure of physical layouts: Ispd 2022 contest,” in Proceedings of International Symposium on Physical Design, pp. 221–228, 2022.
[2] Innovus. https://www.cadence.com/en_US/home/tools/digital-design-and-signoff/ soc-implementation-and-floorplanning/innovus-implementation-system.html.
[3] H.-Y. Liu, I. Diakonikolas, M. Petracca, and L. Carloni, “Supervised design space exploration by compositional approximation of pareto sets,” in Proceedings of Design Automation Conference, pp. 399–404, 2011.
[4] H. Geng, T. Chen, Q. Sun, and B. Yu, “Techniques for cad tool parameter auto-tuning in physical synthesis: a survey,” in Proceedings of Asia and South Pacific Design Automation Conference, pp. 635–640, 2022.
[5] M. M. Ziegler, H.-Y. Liu, G. Gristede, B. Owens, R. Nigaglioni, and L. P. Carloni, “A synthesis-parameter tuning system for autonomous design-space exploration,” in Proceesings of Design, Automation & Test in Europe Conference & Exhibition, pp. 1148– 1151, 2016.
[6] M. M. Ziegler, H.-Y. Liu, and L. P. Carloni, “Scalable auto-tuning of synthesis parameters for optimizing high-performance processors,” in Proceedings of International Symposium on Low Power Electronics and Design, pp. 180–185, 2016.
[7] J. Kwon, M. M. Ziegler, and L. P. Carloni, “A learning-based recommender system for autotuning design flows of industrial high-performance processors,” in Proceedings of Design Automation Conference, 2019.
[8] Z. Xie, G.-Q. Fang, Y.-H. Huang, H. Ren, Y. Zhang, B. Khailany, S.-Y. Fang, J. Hu, Y. Chen, and E. C. Barboza, “Fist: A feature-importance sampling and tree-based method for automatic design flow parameter tuning,” in Proceedings of Asia and South Pacific Design Automation Conference, pp. 19–25, 2020.
[9] A. Agnesina, K. Chang, and S. K. Lim, “Vlsi placement parameter optimization using deep reinforcement learning,” in Proceedings of international Conference on Computer-Aided Design, 2020.
[10] V. Colizza, A. Flammini, M. A. Serrano, and A. Vespignani, “Detecting rich-club ordering in complex networks,” Nature Physics, vol. 2, no. 2, pp. 110–115, 2006.
[11] D. J. Watts and S. H. Strogatz, “Collective dynamics of`small-world'networks,” Nature, vol. 393, no. 6684, pp. 440–442, 1998.
[12] R. Caruana, N. Karampatziakis, and A. Yessenalina, “An empirical evaluation of supervised learning in high dimensions,” in Proceedings of international Conference on Machine Learning, pp. 96–103, 2008.
[13] H.-Y. Liu and L. P. Carloni, “On learning-based methods for design-space exploration with high-level synthesis,” in Proceedings of Design Automation Conference, 2013.
[14] L. Breiman, “Random forests,” Machine Learning, vol. 45, pp. 5–32, 2001.
[15] J. H. Friedman, “Greedy function approximation: a gradient boosting machine,” Annals of Statistics, vol. 29, no. 5, pp. 1189–1232, 2001.
[16] L. Clark, V. Vashishtha, L. Shifren, A. Gujja, S. Sinha, B. Cline, C. Ramamurthy, and G. Yeric, “Asap7: A 7-nm finfet predictive process design kit,” Microelectronics Journal, vol. 53, pp. 105–115, 07 2016.
[17] M. Eslami, J. Knechtel, O. Sinanoglu, R. Karri, and S. Pagliarini, “Benchmarking advanced security closure of physical layouts: Ispd 2023 contest,” in Proceedings of International Symposium on Physical Design, pp. 256–264, 2023.
 
 
 
 
第一頁 上一頁 下一頁 最後一頁 top
* *