|
[1] I.-J. L. Y.-H. W. W.-H. C. Kai-Shun Hu, Hao-Yu Chi and Y.-T. Hsieh, “2023 iccad cad contest problem b: 3d placement with macros.,” 2023 ICCAD CAD Contest Problem B., 2023. [2] J. Lu, P. Chen, C.-C. Chang, L. Sha, D. J.-H. Huang, C.-C. Teng, and C.-K. Cheng, “eplace: Electrostatics based placement using nesterov’s method,” in 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), pp. 1–6, 2014. [3] J. Lu, P. Chen, C.-C. Chang, L. Sha, D. J.-H. Huang, C.-C. Teng, and C.-K. Cheng, “Eplace: Electrostatics-based placement using fast fourier transform and nesterov’s method,” ACM Trans. Des. Autom. Electron. Syst., vol. 20, mar 2015. [4] J. Lu, H. Zhuang, P. Chen, H. Chang, C.-C. Chang, Y.-C. Wong, L. Sha, D. Huang, Y. Luo, C.-C. Teng, and C.-K. Cheng, “eplace-ms: Electrostatics-based placement for mixed-size circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 5, pp. 685–698, 2015. [5] Y. Jiang, X. He, C. Liu, and Y. Guo, “An effective analytical 3d placer in monolithic 3d ic designs,” in 2015 IEEE 11th International Conference on ASIC (ASICON), pp. 1–4, 2015. [6] S. Panth, K. Samadi, Y. Du, and S. K. Lim, “Shrunk-2-d: A physical design methodology to build commercial-quality monolithic 3-d ics,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 10, pp. 1716–1724, 2017. [7] B. W. Ku, K. Chang, and S. K. Lim, “Compact-2d: A physical design methodology to build two-tier gate-level 3-d ics,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 6, pp. 1151–1164, 2020. [8] S. Panth, K. Samadi, Y. Du, and S. K. Lim, “Placement-driven partitioning for congestion mitigation in monolithic 3d ic designs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 4, pp. 540–553, 2015. [9] K. Chang, S. Sinha, B. Cline, R. Southerland, M. Doherty, G. Yeric, and S. K. Lim, “Cascade2d: A design-aware partitioning approach to monolithic 3d ic with 2d commercial tools,” in 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 1–8, 2016. [10] M.-K. Hsu, V. Balabanov, and Y.-W. Chang, “Tsv-aware analytical placement for 3-d ic designs based on a novel weighted-average wirelength model,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 4, pp. 497–509, 2013. [11] W. C. Naylor, R. A. Donelly, and L. Sha, “Non-linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer,” 2001. [12] G. Luo, Y. Shi, and J. Cong, “An analytical placement framework for 3-d ics and its extension on thermal awareness,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 4, pp. 510–523, 2013. [13] T. F. Chan, J. Cong, J. R. Shinnerl, K. Sze, and M. Xie, “Mpl6: Enhanced multilevel mixed-size placement,” in Proceedings of the 2006 International Symposium on Physical Design, ISPD ’06, (New York, NY, USA), p. 212–214, Association for Computing Machinery, 2006. [14] J. Cong and G. Luo, “A multilevel analytical placement for 3d ics,” in 2009 Asia and South Pacific Design Automation Conference, pp. 361–366, 2009. [15] J. Lu, H. Zhuang, I. Kang, P. Chen, and C.-K. Cheng, “Eplace-3d: Electrostatics based placement for 3d-ics,” in Proceedings of the 2016 on International Symposium on Physical Design, ISPD ’16, (New York, NY, USA), p. 11–18, Association for Computing Machinery, 2016. [16] P. Spindler, U. Schlichtmann, and F. M. Johannes, “Abacus: Fast legalization of standard cell circuits with minimal movement,” in Proceedings of the 2008 international symposium on Physical design, pp. 47–53, 2008. [17] C.-K. Cheng, A. B. Kahng, I. Kang, and L. Wang, “Replace: Advancing solution quality and routability validation in global placement,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 9, pp. 1717–1730, 2019. [18] M.-K. Hsu, Y.-W. Chang, and V. Balabanov, “Tsv-aware analytical placement for 3d ic designs,” in 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), pp. 664– 669, 2011. [19] Gurobi Optimization, LLC, “Gurobi Optimizer Reference Manual,” 2023. |