減少邏輯電路中的及閘數量有益於密碼學、安全、量子計算等領域的應用。目前針對這個優化問題提出的最先進的方法是套用一個包含重寫、重構和重新替換等技術的合成流程。雖然實驗結果令人印象深刻，但仍然遺留許多能夠進一步優化的機會。在此論文中，我們提出了一個利用邏輯無關項來減少邏輯電路中及閘數量的方法。此外，我們也提出一個結合最先進的方法的增強式合成流程。實驗使用的測試電路是來自洛桑聯邦理工學院和密碼學領域，並且經過之前研究方法的優化。實驗結果顯示，我們的方法能進一步減少邏輯電路中至多25\%的及閘數量。而對於增強式合成流程的實驗，相較於最先進的方法，在密碼學的測試電路集中，我們達到將近十倍的加速，並擁有和其抗衡的優化結果。

Reducing the number of AND gates in logic networks benefits the applications in cryptography, security, and quantum computing. The state-of-the-art to this optimization problem applied a synthesis flow including rewriting, refactoring, and resubstitution. Although the result was impressive, there remained some opportunities to be optimized further. This work proposes a don’t-care-based approach to reduce the number of AND gates further in the network. Furthermore, this work also proposes an enhanced synthesis flow by integrating our approach with the state-of-the-art. The experiments were performed on a set of well-optimized EPFL and cryptography benchmarks obtained by previous works. The experimental results show that our approach can further reduce up to 25\% of the number of AND gates in the network. For the experiments about the enhanced synthesis flow, we achieve a speedup of almost 10X on average for the cryptography benchmarks while having competitive results as compared to the flow in the state-of-the-art.

中文摘要
英文摘要
誌謝辭
目錄
1. Introduction --------------------------------------------------- 1
2. Background ----------------------------------------------------- 5
2.1 Satisfiability Don't-Cares and Observability Don't-Cares --- 5
2.2 Stuck-At Fault --------------------------------------------- 6
2.3 Boolean Satisfiability Problem ----------------------------- 7
3. An Example of the Proposed DC-based Approach ------------------- 9
4. Proposed Approach ---------------------------------------------- 11
4.1 SDCs & ODCs ------------------------------------------------ 11
4.2 Node Merging & Node Addition and Removal ------------------- 15
4.3 Overall Flow of the Proposed Approach ---------------------- 19
5. Experimental Results ------------------------------------------- 21
5.1 Improvement on the Well-Optimized Benchmarks --------------- 22
5.2 The Proposed Enhanced Synthesis Flow ----------------------- 24
6. Conclusion ----------------------------------------------------- 26

1. M. R. Albrecht, C. Rechberger, T. Schneider, T. Tiessen, and M. Zohner, “Ciphers for MPC and FHE,” in Proc. Eurocrypt, pp. 430–454, 2015.
2. M. Amy, D. Maslov, M. Mosca, and M. Roetteler, “A meet-in-the-middle algorithm for fast synthesis of depth-optimal quantum circuits,” IEEE Trans. on Computer-Aided Design, vol. 32, no. 6, pp. 818–830, 2013.
3. L. Amaru, M. Soeken, P. Vuillod, J. Luo, A. Mishchenko, J. Olson, R. Brayton, and G. De Micheli, “Improvements to Boolean resynthesis,” in Proc. DATE, pp. 755–760, 2018.
4. J. Boyar and R. Peralta, “Tight bounds for the multiplicative complexity of symmetric functions,” Theoretical Computer Science, vol. 396, no. 1–3, pp. 223–246, 2008.
5. J. Boyar and R. Peralta, “A small depth-16 circuit for the AES S-Box,” in Proc. IFIP SEC, pp. 287–298, 2012.
6. J. Boyar, P. Matthews, and R. Peralta, “Logic minimization techniques with applications to cryptology,” Journal of Cryptology, vol. 26, no. 2, pp. 280–312, 2013.
7. J. Cong and Y. Ding, “FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs,” IEEE Trans. on Computer-Aided Design, vol. 13, no. 1, pp. 1-12, 1994.
8. Y.-C. Chen and C.-Y. Wang, “Fast detection of node mergers using logic implications,” in Proc. ICCAD, pp. 785-788, 2009.
9. Y.-C. Chen and C.-Y. Wang, “Fast node merging with don’t cares using logic implications,” IEEE Trans. on Computer-Aided Design, pp.1827-1832, 2010.
10. Y.-C. Chen and C.-Y. Wang, “Node addition and removal in the presence of don’t cares,” in Proc. DAC, pp. 505-510, 2010.
11. Y.-C. Chen and C.-Y. Wang, "Logic restructuring using node addition and removal," IEEE Trans. on Computer-Aided Design, vol. 31, no. 2, pp. 260-270, 2012.
12. M. Chase, D. Derler, S. Goldfeder, C. Orlandi, S. Ramacher, C. Rechberger, D. Slamanig, and G. Zaverucha, “Post-quantum zero-knowledge and signatures from symmetric-key primitives,” in Proc. CCS, pp. 1825–1842, 2017.
13. C. Calik, M. S. Turan, and R. Peralta, “The multiplicative complexity of 6-variable Boolean functions,” Cryptography and Communications, vol. 11, no. 1, pp. 93–107, 2019.
14. S. Jang, K. Chung, A. Mishchenko, and R. Brayton, “A power optimization toolbox for logic synthesis and mapping,” in Proc. IWLS'09, pp. 1-8, 2009.
15. V. Kolesnikov and T. Schneider, “Improved garbled circuit: free XOR gates and applications,” in Proc. ICALP, pp. 486–498, 2008.
16. A. Mishchenko, B. Steinbach, and M. Perkowski, “An algorithm for bi-decomposition of logic functions,” in Proc. DAC, pp. 103–108, 2001.
17. A. Mishchenko and R. K. Brayton, “SAT-based complete don't-care computation for network optimization,” in Proc. DATE, pp. 412-417, 2005.
18. M. Miller and M. Soeken, “An algorithm for linear, affine and spectral classification of Boolean functions,” International Workshop on Boolean Problems, pp. 237–254, 2018.
19. G. Meuli, M. Soeken, E. Campbell, M. Roetteler, and G. De. Micheli, “The role of multiplicative complexity in compiling low T-count oracle circuits,” in Proc. ICCAD, pp. 1-8, 2019.
20. H. Riener, W. Haaswijk, A. Mishchenko, G. De Micheli, and M. Soeken, “On-the-fly and DAG-aware: rewriting Boolean networks with exact synthesis,” in Proc. DATE, pp. 1649-1654, 2019.
21. M. Soeken, E. Testa, and D. M. Miller, “A hybrid method for spectral translation equivalent Boolean functions,” in Proc. PACRIM, pp. 1-6, 2019.
22. M. S. Turan and R. Peralta, “The multiplicative complexity of Boolean functions on four and five variables,” in Lightweight Cryptography for Security and Privacy, pp. 21–33, 2015.
23. G. S. Tseytin, “On the complexity of derivation in propositional calculus,” in Studies in Constructive Mathematics and Mathematical Logic, Part II (Seminars in Mathematics), A. O. Slisenko (Ed.), Consultants Bureau, New York, pp. 115–125, 1970.
24. E. Testa, M. Soeken, L. Amaru and G. De. Micheli, “Reducing the multiplicative complexity in logic networks for cryptography and security applications,” in Proc. DAC, pp. 1-6, 2019.
25. E. Testa, M. Soeken, H. Riener, L. Amaru and G. De. Micheli, “A logic synthesis toolbox for reducing the multiplicative complexity in logic networks,” in Proc. DATE, pp. 568-573, 2020.
26. Berkeley Logic Synthesis and Verification Group, ABC: a system for synthesis and verification, [Online]. Available: http://people.eecs.berkeley.edu/~alanmi/abc/.
27. “Kissat.” [Online]. Available: http://fmv.jku.at/kissat/.