全數位鎖相迴路可在數位系統中實現高精準度的鎖相和時脈訊號生成。本論文介紹了一種創新的全數位鎖相迴路，它採用穩健的延遲線配置，可增強系統在不斷變化的環境條件下的彈性。所提出的全數位鎖相迴路整合了一對延遲線，我們稱為乒乓型延遲線，以動態交換機制運行，允許在不影響環路運行完整性的情況下實現較寬的頻率追蹤範圍。此外，我們使用了一次性的動態校正策略來解決迴路中多路復用器的延遲時間會有不匹配的問題。在供應電壓變化的情況下，包括在 15 微秒內電壓從1伏特驟降至0.97伏特，所提出的全數位鎖相迴路表現出穩定的性能，突顯了其在極端應用中的潛力。所提出的全數位鎖相迴路在使用90nm製程，面積為 0.04 平方毫米，輸出時脈頻率範圍為 0.45GHz 至 1.45GHz。當輸出時脈為1GHz 時功耗僅為 3.49mW。

The All-digital Phase Locked Loop (ADPLL) is to achieve high-precision phase locking and clock generation in digital systems. This thesis presents an innovative ADPLL with a robust delay line configuration that enhances system resilience across changing environmental conditions. The proposed ADPLL integrates a pair of delay lines, called ping-pong delay line, which operates in a dynamic swapping mechanism, allowing a wide frequency tracking range without compromising the integrity of the loop operation. In addition, we implement a one-time dynamic calibration scheme to address the issue of mismatched delay times of the multiplexers in the loops. Under the VDD-changing scenario, which includes a precipitous voltage drop from 1V to 0.97V within 15 microseconds, the proposed ADPLL demonstrated consistent performance, highlighting its potential for extreme applications. The proposed ADPLL utilizes 90nm process and occupies an area of 0.04mm2. Its output clock frequency ranges from 0.45GHz to 1.45GHz, consuming only 3.49mW of power at 1GHz.

Abstract i
摘要 ii
誌謝 iii
Content iv
List of Figures v
List of Tables vii
Chapter 1 Introduction 1
1.1 Introduction 1
1.2 Thesis Organization 4
Chapter 2 Preliminaries 5
2.1 Specification of Baseline ADPLL 5
2.2 Architecture of Baseline ADPLL 5
2.3 Previous Work of Tackling Segment-jumping Problem 8
2.4 Objective of This Work 12
Chapter 3 Proposed New Ping-pong Scheme for ADPLL 14
3.1 Ping-pong ADPLL with Static Calibration 14
3.2 Ping-pong ADPLL with Dynamic Calibration 20
Chapter 4 Simulation Results 24
4.1 Simulation Results of Baseline ADPLL 24
4.2 Simulation Results of Ping-pong ADPLL with Static Calibration 27
4.3 Simulation Results of Ping-pong ADPLL with Dynamic Calibration 30
Chapter 5 Conclusion 38
References 39

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