本論文提出一個十二位元每秒取樣一億次的連續漸進式類比數位轉換器，在高速操作的連續漸進式類比數位轉換器，由於每次比較的時間非常短，常常在C-DAC電壓還沒穩定的時候就必須要做下一次的比較，因此C-DAC電壓穩定的問題嚴重影響電路的效能，也限制了電路的操作速度，這邊採用二進位重組加權電容陣列與數位錯誤校正電路去避免錯誤的比較結果帶來錯誤的轉換結果，同時比較器可以在C-DAC還沒穩定的時候先做比較，以提升電路操作速度；加上回切電容架構去避免不必要的電容切換，也避免電容容值失真時帶來的非線性行為。
使用TSMC 65nm 1P9M製程，在供應電壓為1.2V，在高頻接近尼奎斯特頻率之下，輸入訊號為49.6094 MHz，訊噪失真比（SNDR）為72.2 dB，有效位元數（ENOB）為11.69 bits，平均消耗功率為2.461 mW。在低頻輸入訊號為11.3281 MHz，訊噪失真比（SNDR）為72.4 dB，有效位元數（ENOB）為11.74 bits， 平均消耗功率為2.227 mW，核心電路面積為0.1084平方公釐。

This thesis is a 12-bit 100 MS/s SAR ADC. In high-speed operation of SAR ADC, due to the very short time per comparison cycle, omparison often need to be made before the C-DAC voltage stabilizes. This issue severely affects the circuit's performance and limits its operating speed. To address this, a binary search with recombination and digital error correction circuit are adopted to avoid wrong comparison outcome result in wrong conversion output. Additionally, the comparator can perform comparison before the C-DAC voltage stabilize, thereby improving the circuit's operating speed. Furthermore, correlated-reversed switching is employed to avoid unnecessary capacitor switching and prevent non-linear effect due to capacitor mismatch.
Using TSMC 65nm 1P9M process, the supply voltage is 1.2 V. Operating at high frequency close to the Nyquist frequency, the input signal is 49.6094 MHz. The SNDR is 72.2 dB, ENOB is 11.69 bits, and the average power consumption is 2.461 mW. At low frequencies, the input signal is 11.3281 MHz. The SNDR is 72.4 dB, ENOB is 11.74 bits, and the average power consumption is 2.227 mW. The core circuit area is 0.1084 mm2.

摘要 I
Abstract II
誌謝 III
Table of Contents IV
List of Figures VIII
List of Tables XII

Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Organization of The Thesis 2

Chapter 2 Fundamental of ADC 3
2.1 Academic Terminology 3
2.1.1 Resolution 3
2.1.2 Least Significant Bit 4
2.1.3 Sampling and Quantization 4
2.1.4 Quantization Error 5
2.2 Static Characteristics 6
2.2.1 Offset Error 6
2.2.2 Gain Error 7
2.2.3 Differential Nonlinearity 8
2.2.4 Integral Nonlinearity 9
2.3 Dynamic Characteristics 10
2.3.1 Signal to Noise Ratio 10
2.3.2 Signal to Noise and Distortion Ratio 11
2.3.3 Effective Number of Bits 11
2.3.4 Spurious Free Dynamic Range 11
2.3.5 Dynamic Range 12
2.3.6 Total Harmonic Distortion 12
2.4 Analog to Digital Converter Comparison 13
2.4.1 Flash ADC 13
2.4.2 Pipelined ADC 14
2.4.3 SAR ADC 16

Chapter 3 The Technique of ADC Design 18
3.1 Limitation of Speed 18
3.2 Synchronous and Asynchronous 19
3.3 Top-Plate Sampling and Bottom-Plate Sampling 20
3.4 Capacitor Switching Algorithm 21
3.4.1 Conventional Switching Algorithm 21
3.4.2 Split Capacitor Switching Algorithm 23
3.4.3 Monotonic Capacitor Switching Algorithm 25
3.4.4 Merged Capacitor Switching Algorithm 27
3.4.5 Bidirectional Capacitor Switching Algorithm 28
3.5 Error Tolerance and Error Correction 30
3.5.1 Conventional Binary Search 30
3.5.2 Nonbinary Search 31
3.5.3 Binary Search with Compensation 31
3.5.4 Binary Search with Recombination 32

Chapter 4 A 12-bit 100MS/s SAR-ADC with DEC and CRS 34
4.1 Architecture 34
4.2 Sample and Hold 35
4.2.1 Circuit Principle 35
4.2.2 Design Consideration 36
4.2.3 Circuit Implementation 42
4.2.4 Simulation Results 45
4.3 Comparator 46
4.3.1 Circuit Principle 46
4.3.2 Design Consideration 48
4.3.3 Circuit Implementation 51
4.3.4 Simulation Results 54
4.4 Capacitor Array 56
4.4.1 Capacitor Structure Selection 56
4.4.2 Capacitor Array Weighting 59
4.4.3 Capacitor Layout Planning 62
4.5 Digital Error Correction 63
4.6 Digital Logic Control 64
4.6.1 Clock Generation Logic 65
4.6.2 Control Logic 67

Chapter 5 Simulation result 70
5.1 Pre-Simulation before layout 70
5.2 Post-Simulation after layout 72

Chapter 6 Conclusion and Future work 76
Reference 77

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