隨著科技的演進，類比數位轉器在各方面的應用都非常多，在商業用上特別注重功耗，在此已經有許多相關研究，本論文實現200MS/s 10位元的連續漸進式類比數位轉換器，選擇其架構原因是在中高速和中高解析度是最省電的，在設計過程中也會提到此單一架構下無法提高速度和解析度的原因。
本論文採用台積電所提供之六十五奈米 CMOS 製程進行模擬設計，論文開頭為介紹類比數位轉換器會使用到的相關參數和專有名詞，在觀察模擬結果時能夠快速判斷轉換器的性能結果，接著介紹不同的轉換器架構；下一章討論到連續漸進式類比數位轉換器的操作原理和相關應用技術，也簡單陳述其限制；第四章則說明電路的實現，以及設計考量；第五章呈現模擬結果；最後做總結和附上參考資料。

With the evolution of technology, the application of analog-to-digital converter (ADC) is widespread in various fields, with particular emphasis on power consumption in commercial use. There have been many related studies in this area. In this thesis, a 200MS/s 10-bit successive approximation ADC (SAR ADC) is implemented, and the chosen architecture is known to be the most power-efficient for medium-high speed and medium-high resolution applications. The reasons for the inability to improve speed and resolution under this single architecture will also be discussed in the design process.
The thesis utilizes the 65nm CMOS process provided by TSMC for simulation and design. The introduction of the thesis provides relevant parameters and proprietary terms used in ADC design, which enables quick assessment of the performance results when observing the simulation results. Different ADC architectures are then introduced. The next chapter discusses the operating principles and related techniques of successive approximation ADCs, as well as their limitations. The fourth chapter explains the circuit implementation and design considerations. The fifth chapter presents the simulation results. Finally, conclusions are drawn and references are included.

摘要)----i
ABSTRACT)----ii
誌謝)----iii
目錄)----iv
圖目錄)----vii
表目錄)----xi
第一章 簡介)----1
1.1 研究動機(Motivation)----1
1.2 章節說明)----2
第二章 類比數位轉換器相關介紹)----3
2.1 類比數位轉換器專有名詞和參數)----3
2.1.1 專有名詞)----3
2.1.2 靜態參數(Static Parameter))----6
2.1.3 動態參數(Dynamic Parameter))----7
2.2 類比數位轉換器種類(Types of ADC ))----10
2.2.1 快閃式類比轉換器(Flash ADC))----10
2.2.2 導管式類比數位轉換器(Pipeline ADC))----11
2.2.3 連續漸進式類比數位轉換器(SAR ADC))----12
第三章 中高速連續漸進式類比數位轉換器)----14
3.1 SAR ADC 操作原理(SAR ADC Operation)----14
3.1.1 單端與雙端(Single-Ended Signal VS Differential Signal)----15
3.1.2 電容陣列訊號取樣(Cap-Array Signal sampling)----15
3.1.3 電荷重新分配(Charge Redistribution)----17
3.1.4 SAR ADC切換過程(SAR ADC Switching)----17
3.1.5 電容切換法能量分析(Switching Cap Energy Analysis )----25
3.2 SAR ADC 速度限制(SAR ADC Speed Limatation)----26
3.2.1 電容陣列和穩定時間(Cap Array & Settling time)----27
3.2.2 雜訊(Noise)----29
3.3 逐次逼近法(Successive-approximation Algorithm)----29
3.3.1 二進制搜尋(Binary Search)----30
3.3.2 非二進制搜尋(Non-binary Search)----31
3.3.3 具錯誤校正冗餘逼近法 (Redundant Approximation with Error correction)----31
第四章 10位元200-MS/s SAR ADC----33
4.1 取樣保持電路(Sample & Hold Circuit)----33
4.2 電容矩陣數位類比轉換器(C-DAC)----37
4.3 比較器(Comparator)----40
4.4 數位電路(Digital Circuit)----47
4.4.1 SAR邏輯控制電路(SAR Logic Control Circuit)----47
4.4.2 數位錯誤校正電路(Digital Error Correction Circuit)----50
第五章 模擬結果(Simulation Result)----51
5.1 布局前模擬(Pre-sim)----51
5.2 布局後模擬(Post-sim)----52
第六章 結論(Conclusion)----56
6.1 總結(Summary)----56
參考資料----57

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