基於標準細胞元件庫設計的數位控制振盪器（DCO）是基於標準細胞元件庫設計的相位鎖定迴路（PLL）系統中的關鍵元件，對於晶片上高速時脈訊號生成至關重要。然而，以往的基於標準細胞元件庫設計的數位控制振盪器存在幾個缺點，包括非線性的數位控制振盪器周期特性、不均勻的時間分辨率以及輸出時脈周期間隙風險。在我們的工作中，我們通過使用鎖存可變電容單元來解決和克服這些問題。通過佈局後模擬，我們證明了我們的數位控制振盪器可以在所有五個工藝角落內與 -40° 到150°C 的極端溫度條件下保證無間隙的輸出時脈周期範圍。更重要的是，我們的設計在整個時脈周期範圍內保持穩定的1皮秒時間分辨率。
除了這些改進之外，當我們將數位控制振盪器集成到相位鎖定迴路中時，我們觀察到輸出時脈峰對峰的抖動從10.86皮秒顯著減少到6.07皮秒。這一抖動性能的改進突顯了我們設計的有效性。此外，我們的數位控制振盪器基於標準細胞元件庫設計，使其具有更大的靈活性和適應性。我們演示了一次製程工藝遷移，並編寫了一個綜合指南，以便於理解和實施不同製程工藝之間的轉換。這個指南是一個寶貴的資源，旨在幫助那些希望順利高效地進行製程工藝變遷的人。

A cell-based Digitally Controlled Oscillator (DCO) is a key component in cell-based Phase-Locked Loop (PLL) systems, crucial for on-chip high-speed clock generation. However, previous iterations of cell-based DCOs have faced several drawbacks, including a nonlinear DCO period profile, non-uniform time resolution, and the risk of output clock period gaps. In our work, we address and overcome these issues by employing latch-based varactor cells. Through post-layout simulation, we have demonstrated that our DCO can ensure a gapless output clock period range across all five process corners, even under the most extreme temperature conditions ranging from -40˚C to 150˚C. Furthermore, our design maintains a stable time resolution of 1ps across the entire clock period range.
In addition to these improvements, when we integrated our DCO into the PLL, we observed a significant reduction in the output clock peak-to-peak jitter, from 10.86ps down to 6.07ps. This improvement in jitter performance highlights the effectiveness of our design. Moreover, the cell-based design of our DCO allows for greater flexibility and adaptability. We successfully demonstrated a CMOS process migration of our proposed design and have compiled a comprehensive guideline to facilitate the understanding and implementation of transitions between different CMOS processes. This guideline is a valuable resource for those looking to navigate the complexities of CMOS process variations, ensuring smooth and efficient migrations.

Abstract...........................................................ii
摘要...............................................................iii
Content............................................................iv
List of Figures....................................................vi
List of Tables.....................................................vii
Chapter 1 Introduction.............................................1
1.1 Introduction...................................................1
1.2 Thesis Organization............................................7
Chapter 2 Preliminaries............................................8
2.1 The Delay Tuning Techniques for DCO............................8
2.2 Architecture and Characteristics of Prior DCO..................10
Chapter 3 Proposed DCO Architecture................................12
3.1 Previous DCO Techniques........................................12
3.2 DCO Architecture using Latch-Based Varactor Cells..............12
3.3 Proposed DCO Architecture with Path-Selection Part.............17
Chapter 4 Simulation Results.......................................19
4.1 DCO Simulation and Characteristic..............................19
4.2 ADPLL Simulation and Characteristic............................22
Chapter 5 Process Migration to a 40nm CMOS Process.................25
5.1 Configuration Parameters of Proposed DCO.......................25
5.2 Guideline for DCO Migrated to 40nm CMOS Process................26
5.3 DCO Period Profile Using a 40nm CMOS Process and Performance under Extreme Conditions.................................................28
5.4 Layouts and Simulation Result of ADPLL with Proposed DCO.......30
5.5 Comparison with Other Related Works of ADPLL...................33
Chapter 6 Conclusion...............................................35
References.........................................................36

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