高頻交易在金融市場中以極快的速度進行買賣，以追求套利機會。在高頻
交易中，時間尤為寶貴，即使毫秒級的延遲也可能對套利結果產生巨大的影響。
本研究致力於研究封包處理和傳輸，並與合作廠商皓德盛科技有限公司，提出
了一種基於現場可程式化邏輯閘陣列的多通道連線高頻交易系統的封包處理器，
應用於日本市場。該封包處理器負責解析來自交易所的市場行情和訂單回報，
同時支援多通道連線，快速生成封包並以序列方式發送至交易所，以實現快速
下單之目的。該處理器運行於 156.25 兆赫的時脈頻率下，搭載乙太網路實體收
發器，從接收封包到解析完成的延遲僅為 198.4 奈秒，而從生成封包到傳送的延
遲僅 70.4 奈秒。相較於傳統軟體交易系統，效能提升了 100 倍以上。

此外，本研究通過環境模擬測試該封包處理器，建立了一個交易所模型，
模擬了實際交易所的環境，並檢查每個封包傳送的正確性，以確保連線的穩定。
在 1000 次訂單觸發的測試中，該封包處理器成功生成和發送各種類型的訂單，
並成功接收了交易所模型返回的訂單成功回報。這項研究的結果顯示，這個基
於現場可程式化邏輯閘陣列的封包處理器在高頻交易環境中具有卓越的性能，
可以有效地支持快速下單和高頻交易策略的執行，有望為金融市場的高頻交易
者提供實質的競爭優勢。

High-frequency trading involves buying and selling financial assets at incredibly fast speeds to pursue arbitrage opportunities in the financial markets. This study focuses on packet processing and, in collaboration with Vsense FinTech Inc., presents an FPGA-based packet processor with multi-channel connection for high-frequency trading system. This packet processor is applied in the Japanese market. The packet processor is responsible for parsing market data and order reports from the exchange, while simultaneously supporting multiple channel connections to rapidly generate packets and transmit them sequentially to the exchange, for the purpose of achieving fast order execution. This processor operates at a clock frequency of 156.25 MHz and is equipped with an Ethernet physical layer transceiver. The latency from packet reception to parsing completion is as low as 198.4 ns, and the latency from packet generation to transmission is a mere 70.4 ns. This results in a performance improvement of over 100 times compared to traditional software trading systems.

Furthermore, this research rigorously tests the packet processor through environmental simulations, establishing an exchange model that simulates the conditions of an actual exchange. It verifies the accuracy of each packet transmission to ensure stable connectivity. In a test involving 1000 order triggers, the packet processor successfully generated and sent various types of orders and received successful order acknowledgments from the exchange model. The results of this study demonstrate that this FPGA-based packet processor excels in high-frequency trading environments, effectively supporting rapid order placement and the execution of high-frequency trading strategies. It holds the potential to provide a substantial competitive advantage to high-frequency traders in the financial markets.

3 Proposed FPGA-based Packet Processor of HFT System 19
3.1 System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 Network Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2.1 Network Layer Overview . . . . . . . . . . . . . . . . . . . . 22
3.2.2 Network Connection Manager Modification . . . . . . . . . . . 25
3.3 Financial Protocol Decoder . . . . . . . . . . . . . . . . . . . . . . . . 27
3.3.1 Market Decoder . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.3.2 Order Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.4 Modularized Financial Protocol Encoder . . . . . . . . . . . . . . . . . 37
3.4.1 Finite State Machine . . . . . . . . . . . . . . . . . . . . . . . 39
3.4.2 Payload Generator . . . . . . . . . . . . . . . . . . . . . . . . 41
3.4.3 SN ACK Generator . . . . . . . . . . . . . . . . . . . . . . . . 44
3.4.4 Checksum Generator . . . . . . . . . . . . . . . . . . . . . . . 46
3.4.5 Ethernet Frame Generator . . . . . . . . . . . . . . . . . . . . 47
3.4.6 Frame Serializer . . . . . . . . . . . . . . . . . . . . . . . . . 49
4 Implementation and Evaluation Results 52
4.1 Experimental Environment . . . . . . . . . . . . . . . . . . . . . . . . 52
4.2 Functional Verification . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.3 Utilization of Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.4 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5 Conclusion and Future Works 66
5.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.2 Future Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Bibliography 68

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