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作者(中文):張之懿
作者(外文):Chang, Chih-Yi
論文名稱(中文):以網格搜索法與平行運算提升晶圓級封裝可靠度預估之AI訓練效率研究
論文名稱(外文):Using Grid Search Methods and Parallel Computing to Reduce AI Training Time for Reliability Lifetime Prediction of Wafer-Level Packaging
指導教授(中文):江國寧
指導教授(外文):Chiang, Kuo-Ning
口試委員(中文):陳志明
劉德騏
鄭仙志
口試委員(外文):Chen, Chih Ming
Liu, De Shin
Cheng, Hsien Chie
學位類別:碩士
校院名稱:國立清華大學
系所名稱:動力機械工程學系
學號:110033631
出版年(民國):112
畢業學年度:111
語文別:中文
論文頁數:101
中文關鍵詞:晶圓級封裝有限單元分析熱循環負載可靠度預估機器學習平行運算網格搜索法
外文關鍵詞:Wafer Level PackagingFinite Element AnalysisThermal Cycle LoadReliability EstimationMachine LearningParallel ComputingGrid Search
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隨著科技的發展以及人們對行動裝置需求增加,隨著時間的推移,電子產品
變得越來越輕薄、小巧且功能多樣化。因此,電子封裝的目標是朝向微小化發展。
為了維持摩爾定律,在過去幾十年來,電子封裝技術已經經過兩次的革新,第一次
革新是表面黏著技術(Surface Mount Technology, SMT),取代了插槽式技術(Pin
Through Hole, PTH),第二次革新是球柵陣列封裝(Ball Grid Array, BGA),取代外
圍接腳封裝,隨著越來越接近摩爾定律的極限,將不同種類的晶片和功能模組結
合成一個封裝的概念促進了第三次革新,稱之為系統型封裝(System in Package,
SiP),也可稱作 3D 異質整合。到了現今晶圓級封裝(Wafer Level Packaging, WLP)為本研究探討結構。
電子封裝在產品上市前必須通過一系列的封裝結構可靠度測試實驗,其中加
速熱循環測試(Accelerated Thermal Cycling Test,ATCT)為一標準且被廣泛運用的
可靠度測驗,然而熱循環測試要花費大量時間與成本,為了跟上市場需求腳步,
運用有限單元數值分析於可靠度測試,使用ANSYS 模擬軟體得到晶圓級封裝結
構的應力分布及破壞情況,再經由經驗公式獲得封裝結構之壽命。
使用有限單元數值分析建立的模型,由於不同研究者之物理觀念有所差異,
且有許多因素考量點的不同,導致模擬的誤差產生,為了減低誤差並節省建構模
型所花費時間,在目前半導體人才不足的情況下,藉由將模擬以及人工智慧中機
器學習的概念合併,透過已經與實驗驗證過的模型建構訓練資料,將資料引入演
算法內後得到一個穩定且全面的預估機器學習模型。
在機器學習模型中,訓練時間為其一研究方向,而網格搜尋時間極少被探討,
兩者相比之下,網格搜尋時間比訓練時間大了許多,因而在本研究中,將以晶圓
級封裝可靠度為例,使用平行運算探討最佳化參數的搜索,使其可全面應用於不
同機器學習演算法,並利用自訂的經驗公式增進網格搜索法的效率,進而提升封
裝產品的上市時間與競爭力。
With the development of technology and people's increasing demand for mobile devices, electronic products are becoming thinner, smaller, and more multi-functional. The goal of electronic packaging is miniaturization. To maintain Moore's Law, in the past few decades, electronic packaging technology has undergone two innovations. The first innovation is Surface Mount Technology (SMT), which replaced slot technology (Pin Through Hole, PTH). The second innovation is the adoption of Ball Grid Array(BGA) packaging, replacing traditional peripheral lead packages. As we approach the limits of Moore's Law, the concept of integrating different types of chips and functional
modules into a single package has facilitated the third revolution known as System in Package (SiP) or 3D heterogeneous integration. In the present day, Wafer Level Packaging (WLP) is the focus of this study in terms of structure.
Electronic packages must pass a series of package structure reliability testing experiments before products heat the market. Among them, Accelerated Thermal Cycling Test (ATCT) is a standard and widely used reliability test. However, thermal cycling tests cost a lot of time and money. To keep up with market demand, finite element analysis is used for reliability testing. By using ANSYS simulation software,
we can obtain the stress distribution and damage of the wafer-level packaging structure. And then, the life of the packaging structure is obtained through empirical formulas.
We can use finite element analysis to build the model. Since different researchers have different physical concepts and different considerations. This leads to simulation errors. To reduce errors and save the time spent building models. In the case of deficiencies in semiconductor talents, we can combine the concepts of machine learning
in simulation and artificial intelligence, and build training data through models that have been verified with experiments. A stable and comprehensive predictive machine learning model is obtained after the data is introduced into the algorithm.
In machine learning models, training time is one of the research directions, while grid search time is rarely discussed, both of which have a significant impact on the efficiency of machine learning models. In this study, we take WLCSP as a case study and use parallel computing to discuss the search for optimized parameters, which can be fully applied to different machine learning algorithms. Besides, we use custom empirical formulas to improve the efficiency of grid search methods, thereby improving the time-to-market and competitiveness of packaged products.
摘要--------II
Abstract----III
目錄--------V
圖目錄------VIII
表目錄------XII
1. 第一章 緒論 1
1.1 研究動機 1
1.2 文獻回顧 2
1.3 研究目標 6
2. 第二章 基礎理論 7
2.1 有限單元法基礎理論 7
2.1.1 材料線彈性理論 8
2.1.2 材料非線性理論 11
2.1.3 數值收斂方法與準則 13
2.2 材料應變硬化法 14
2.2.1 等向硬化法則(Isotropic Hardening Rule) 16
2.2.2 動態硬化法則(Kinematic Hardening Rule) 16
2.3 Chaboche 模型 17
2.4 錫球外型預測 19
2.5 封裝體可靠度預測方法 21
2.5.1 Coffin-Manson應變法 21
2.5.2 Darveaux 能量密度法 21
2.5.3 修正型能量密度法 22
2.6 機器學習 23
2.6.1 機器學習演算法 23
2.6.2 資料前處理 24
2.6.3 支持向量迴歸模型 26
2.6.4 理論推導 26
2.6.5 核函數 33
2.6.6 參數學習 34
2.6.7 平行運算 36
3. 第三章 有限單元之模型模擬驗證與分析 38
3.1 有限單元模型基本假設 39
3.2 錫球外型預估 40
3.3 材料參數設定 41
3.4 網格劃分與元素 43
3.5 溫度循環負載設定 44
3.6 有限單元模型建構 45
3.6.1 Test Vehicles 46
3.7 有限單元模擬分析之驗證 52
4. 第四章 研究結果與討論 53
4.1 資料庫的建立 53
4.2 支持向量迴歸模型超參數之設定 56
4.3 網格搜尋法(Grid Search) 57
4.4 二分法(Bisection method) 58
4.5 平面擬合法(Plane fitting) 59
4.5.1 反向梯度下降法(Backward gradient descent) 66
4.6 平行運算與網格搜尋法 68
4.7 超參數公式定義 77
4.7.1 超參數ε 77
4.7.2 超參數γ 85
4.7.3 超參數C 87
5. 結論與未來建議工作 94
6. 參考資料 95

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