隨著近年來市場對電子零件需求大增，對晶片數量及品質的需求也隨之提高。因此高生產效率、高生產品質、低成本的面板級封裝已成為不可或缺的重要電子元件生產方式。隨之而來的問題是，相較於晶圓級封裝，面板級封裝因為面板面積較大，對於製程精準度的要求更高。在完整的製程中可能因為面板加熱不均勻、製作平台水平精度不足、面板各層材料選擇搭配不同、製程溫度與升降溫速率不同等因素。使面板產生環氧樹脂硬化程度不均勻、厚度不均勻、各材料間熱膨脹係數不匹配等問題，進而導致面板級封裝產生非對稱翹曲。
以實際製程而言，要找到面板級封裝適合的材料搭配並根據不同材料選擇找到相符的製程溫度和升降溫速率，需要花費非常大量的時間。因此，此研究將專使用有限元素法(Finite Element Method)建立320mm x 320mm扇出型面板級封裝的三維立體模型，探討在面板級封裝的製程中產生翹曲的因素和製程參數對其的影響。首先，會探討在全彈性模型下，完成後熟化製程後，其玻璃載板的剝離路徑對最終翹曲行為的影響分析，發現在相同的製程參數下，不同的載板剝離路徑會導致最終不同的翹曲圖形。
除了探討面板級封裝在彈性模型下的翹曲行為外，實際製程中，環氧樹脂具有明顯的非線性行為，包含了與時間溫度相關的硬化度、老化效應和與硬化相關的黏彈性機械行為等等。因此，本文中也會探討封膠環氧樹脂的非線性行為，建立包含硬化動力學模型、溫度相關熱膨脹係數模型和黏彈性本構模型的封膠線黏彈性模型。分析其熱壓成型製程溫度、後硬化製程溫度與過程中的升降溫速率等對於最終翹曲行為的影響。另外，也分析在封膠黏彈性模型下，製程中加熱不均勻、厚度不均勻和硬化度不均勻以及使用不同晶片尺寸對最終翹曲行為的影響。
最後使用K-近鄰演算法機器學習模型，來預測面板級封裝在不同幾何尺寸下與不同升降溫速率下，其翹曲值的變化情形。

With the increasing market demand for electronic components in recent years, the need for package quantity and quality has also increased. Therefore, panel-level packaging with high production efficiency, high production quality, and low cost has become an indispensable critical production method for electronic components. But the problem that comes with it is that compared with wafer-level packaging, panel-level packaging requires higher process accuracy due to the larger panel area. Throughout the process, problems such as uneven panel thickness, uneven epoxy curing, and CTE mismatch between different layers of the panel will occur, resulting in asymmetric warpage of the panel-level package. Not only does it affect the yield of electronic packaging, but significant warpage also increases the difficulty of dicing into a single package structure.
As far as the actual process is concerned, it takes a lot of time to find a suitable material combination for panel-level packaging and to find the appropriate process temperature and rates according to the different structures of the panel-level packaging. Therefore, this study will use the Finite Element Method (FEM) to build a 3D model of a 320mm x 320mm fan-out panel-level package to discuss the causes of warpage behavior and the influence of process parameters in the PLP process. First, under the fully elastic model, the influence of the debonding path of the glass carrier after the completion of the post-curing process is discussed. And it is found that under the same process parameters, different carrier removing paths lead to different warpage patterns.
In addition to discussing the warpage behavior of the panel-level package under the elastic model, the epoxy resin has complex nonlinear behavior in the actual process, including the time-temperature-dependent hardening degree, aging effect, and the viscoelastic mechanical behavior related to hardening. Therefore, the nonlinear behavior of encapsulated epoxy resins is also discussed in this paper, so an encapsulation model including a hardening kinetic model, a temperature-dependent thermal expansion coefficient model, and a viscoelastic constitutive model is built to analyze the influence of the compress molding process, the post-mold cure process temperature, and the heating and cooling rate in the process on the final warpage behavior. In addition, under the viscoelastic model, the effect of uneven heating during processing, uneven thickness, uneven degree of hardening, and the use of different chip sizes on the final warpage behavior will be analyzed.
Finally, the K-nearest neighbors (KNN) algorithm machine learning model is used to predict the variation of warpage values in panel-level packaging under different geometric dimensions and cooling rates.

摘要 I
Abstract III
目錄 V
圖目錄 VIII
表目錄 XII
第一章 緒論 1
1.1 簡介 1
1.2 研究動機與研究方法 3
1.3 文獻回顧 4
第二章 基礎理論 12
2.1 有限元素法理論 12
2.1.1 線彈性理論 12
2.2 有限元素法接觸理論 15
2.2.1 拉格朗日乘子法 16
2.2.2 懲罰函數法 16
2.2.3 增廣拉格朗日乘子法 17
2.3 翹曲分析與高分子材料理論 18
2.3.1 熱膨脹係數不匹配 18
2.3.2 等效熱膨脹係數 19
2.3.3 熱固性高分子材料之固化反應 20
2.3.4 P-V-T-C方程式 21
2.3.5 黏彈性行為與黏彈性本構模型 22
2.4 扇出型晶圓級與面板級封裝製程 26
2.5 機器學習 29
2.5.1 資料前處理(Data Preprocessing) 29
2.5.2 機器學習基礎原理 30
2.5.3 分類(Classification)與迴歸(Regression)問題 31
2.5.4 低度擬合(Underfitting)和過度擬合(Overfitting) 32
2.5.5 交叉驗證(Cross-Validation) 34
2.6 K-近鄰演算法(K-Nearest Neighbors) 35
2.6.1 K值 36
2.6.2 距離度量方式 37
2.6.3 權重定義與計算 38
第三章 線彈性模型下翹曲圖形分析 40
3.1 扇出型面板級封裝模型 40
3.2 扇出型面板級封裝之製程模擬 43
3.3 玻璃載板剝離路徑對翹曲圖形影響分析 47
第四章 黏彈性模型下製程參數與翹曲圖形分析 55
4.1 扇出型面板級封裝模型 55
4.2 扇出型面板級之製程模擬 58
4.3 扇出型面板級封裝製程參數對翹曲圖影響分析 60
4.3.1 環氧樹脂壓模成型溫度分析 61
4.3.2 後熟化製程溫度與持溫時間分析 62
4.3.3 升降溫速率分析 63
4.3.4 參數綜合田口方法分析 65
第五章 KNN應用於面板翹曲預測結果 67
5.1 訓練與測試資料建立 67
5.2 訓練與測試資料前處理 69
5.3 面板翹曲KNN模型預測 72
5.3.1 翹曲圖形判別 74
5.3.2 翹曲值預測 78
5.4 結果與討論 85
第六章 結論與未來建議 88
參考文獻 90

參考文獻
[1] H.-W. Liu et al., "Warpage characterization of panel fan-out (P-FO) package," in 2014 IEEE 64th Electronic Components and Technology Conference (ECTC), 2014: IEEE, pp. 1750-1754.
[2] C.-T. Ko et al., "Chip-first fan-out panel-level packaging for heterogeneous integration," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 8, no. 9, pp. 1561-1572, 2018.
[3] J. H. Lau, "Recent advances and trends in fan-out wafer/panel-level packaging," Journal of Electronic Packaging, vol. 141, no. 4, p. 040801, 2019.
[4] T. Braun et al., "Fan-out wafer and panel level packaging as packaging platform for heterogeneous integration," Micromachines, vol. 10, no. 5, p. 342, 2019.
[5] J. H. Lau et al., "Design, materials, process, fabrication, and reliability of fan-out wafer-level packaging," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 8, no. 6, pp. 991-1002, 2018.
[6] N. Kinjo, M. Ogata, K. Nishi, A. Kaneda, and K. Dušek, "Epoxy molding compounds as encapsulation materials for microelectronic devices," Speciality Polymers/Polymer Physics, pp. 1-48, 1989.
[7] C. Tsai, S. Liu, and K. Chiang, "Warpage analysis of fan-out panel-level packaging using equivalent CTE," IEEE Transactions on Device and Materials Reliability, vol. 20, no. 1, pp. 51-57, 2019.
[8] 蔡佳翰, "使用等效熱膨脹係數於扇出型面板級封裝之翹曲研究," 國立清華大學, 2018.
[9] T.-C. Chiu, C.-L. Gung, H.-W. Huang, and Y.-S. Lai, "Effects of curing and chemical aging on warpage—Characterization and simulation," IEEE Transactions on Device and Materials Reliability, vol. 11, no. 2, pp. 339-348, 2011.
[10] S. Montserrat, "Vitrification and physical ageing on isothermal curing of an epoxy resin," Journal of Thermal Analysis and Calorimetry, vol. 37, no. 8, pp. 1751-1758, 1991.
[11] S. R. White, P. Mather, and M. Smith, "Characterization of the cure‐state of DGEBA‐DDS epoxy using ultrasonic, dynamic mechanical, and thermal probes," Polymer Engineering & Science, vol. 42, no. 1, pp. 51-67, 2002.
[12] H. Yu, S. Mhaisalkar, and E. Wong, "Cure shrinkage measurement of nonconductive adhesives by means of a thermomechanical analyzer," Journal of electronic materials, vol. 34, no. 8, pp. 1177-1182, 2005.
[13] M. Harsch, J. Karger-Kocsis, and M. Holst, "Influence of fillers and additives on the cure kinetics of an epoxy/anhydride resin," European Polymer Journal, vol. 43, no. 4, pp. 1168-1178, 2007.
[14] J. Wan, Z.-Y. Bu, C.-J. Xu, B.-G. Li, and H. Fan, "Preparation, curing kinetics, and properties of a novel low-volatile starlike aliphatic-polyamine curing agent for epoxy resins," Chemical Engineering Journal, vol. 171, no. 1, pp. 357-367, 2011.
[15] H. Cai et al., "Curing kinetics study of epoxy resin/flexible amine toughness systems by dynamic and isothermal DSC," Thermochimica Acta, vol. 473, no. 1-2, pp. 101-105, 2008.
[16] R. M. Patel and J. E. Spruiell, "Crystallization kinetics during polymer processing—analysis of available approaches for process modeling," Polymer Engineering & Science, vol. 31, no. 10, pp. 730-738, 1991.
[17] Y. K. Kim and S. R. White, "Stress relaxation behavior of 3501‐6 epoxy resin during cure," Polymer Engineering & Science, vol. 36, no. 23, pp. 2852-2862, 1996.
[18] K. Jansen et al., "Constitutive modeling of moulding compounds [electronic packaging applications]," in 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No. 04CH37546), 2004, vol. 1: IEEE, pp. 890-894.
[19] O. U. Colak and N. Dusunceli, "Modeling viscoelastic and viscoplastic behavior of high density polyethylene (HDPE)," 2006.
[20] T. Braun et al., "From wafer level to panel level mold embedding," in 2013 IEEE 63rd Electronic Components and Technology Conference, 2013: IEEE, pp. 1235-1242.
[21] F. Hou et al., "Experimental verification and optimization analysis of warpage for panel-level fan-out package," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 7, no. 10, pp. 1721-1728, 2017.
[22] S. R. McCann, V. Sundaram, R. R. Tummala, and S. K. Sitaraman, "Flip-chip on glass (FCOG) package for low warpage," in 2014 IEEE 64th Electronic Components and Technology Conference (ECTC), 2014: IEEE, pp. 2189-2193.
[23] F. X. Che, K. Yamamoto, V. S. Rao, and V. N. Sekhar, "Study on warpage of fan-out panel level packaging (FO-PLP) using Gen-3 panel," in 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 2019: IEEE, pp. 842-849.
[24] P. B. Lin et al., "A comprehensive study on stress and warpage by design, simulation and fabrication of RDL-first panel level fan-out technology for advanced package," in 2017 IEEE 67th Electronic Components and Technology Conference (ECTC), 2017: IEEE, pp. 1413-1418.
[25] M.-Y. Tsai, H.-Y. Chang, and M. Pecht, "Warpage analysis of flip-chip PBGA packages subject to thermal loading," IEEE Transactions on Device and Materials Reliability, vol. 9, no. 3, pp. 419-424, 2009.
[26] J. De Vreugd et al., "Effect of postcure and thermal aging on molding compound properties," in 2009 11th Electronics Packaging Technology Conference, 2009: IEEE, pp. 342-347.
[27] D. Belton, "The effect of post-mold curling upon the microstructure of epoxy molding compounds," IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 10, no. 3, pp. 358-363, 1987.
[28] D. Yang, K. Jansen, L. Ernst, G. Zhang, W. Van Driel, and H. Bressers, "Modeling of cure-induced warpage of plastic IC packages," in 5th International Conference on Thermal and Mechanical Simulation and Experiments in Microelectronics and Microsystems, 2004. EuroSimE 2004. Proceedings of the, 2004: IEEE, pp. 33-40.
[29] H. F. Brinson and L. C. Brinson, "Polymer engineering science and viscoelasticity," An introduction, pp. 99-157, 2008.
[30] M. Sadeghinia, K. Jansen, and L. Ernst, "Characterization and modeling the thermo-mechanical cure-dependent properties of epoxy molding compound," International Journal of Adhesion and Adhesives, vol. 32, pp. 82-88, 2012.
[31] M. van Dijk et al., "Simulation challenges of warpage for wafer-and panel level packaging," in 2020 21st International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), 2020: IEEE, pp. 1-6.
[32] F. Che, K. Yamamoto, and V. S. Rao, "Panel Warpage and Die Shift Simulation and Characterization of Fan-Out Panel-Level Packaging," in 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), 2020: IEEE, pp. 2097-2104.
[33] G. Taguchi, "Quality engineering (Taguchi methods) for the development of electronic circuit technology," IEEE Transactions on Reliability, vol. 44, no. 2, pp. 225-229, 1995.
[34] S. K. Karna and R. Sahai, "An overview on Taguchi method," International journal of engineering and mathematical sciences, vol. 1, no. 1, pp. 1-7, 2012.
[35] S. K. Panigrahy, Y.-C. Tseng, B.-R. Lai, and K.-N. Chiang, "An overview of AI-Assisted design-on-Simulation technology for reliability life prediction of advanced packaging," Materials, vol. 14, no. 18, p. 5342, 2021.
[36] 蘇尼拉, "應用人工智慧輔助設計於晶圓級封裝之可靠度壽命預測研究," 博士, 動力機械工程學系, 國立清華大學, 新竹市, 2022. [Online]. Available: https://hdl.handle.net/11296/v46qtw
[37] H. Hsiao and K. Chiang, "AI-assisted reliability life prediction model for wafer-level packaging using the random forest method," Journal of Mechanics, vol. 37, pp. 28-36, 2021.
[38] 陳柏維, "數據分布於集成學習演算法對晶圓級封裝可靠度預估之影響," 碩士, 動力機械工程學系, 國立清華大學, 新竹市, 2021. [Online]. Available: https://hdl.handle.net/11296/h9ec74
[39] P. Chou, H. Hsiao, and K. Chiang, "Failure life prediction of wafer level packaging using DoS with AI technology," in 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 2019: IEEE, pp. 1515-1520.
[40] P. Chou, K. Chiang, and S. Y. Liang, "Reliability assessment of wafer level package using artificial neural network regression model," Journal of Mechanics, vol. 35, no. 6, pp. 829-837, 2019.
[41] C. Yuan, Y.-J. Hong, C.-C. Lee, K.-N. Chiang, and J.-H. Huang, "Application of artificial and recurrent neural network on the steady-state and transient finite element modeling," in 2019 20th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), 2019: IEEE, pp. 1-7.
[42] 傅聖元, "數據及不同結構之循環神經網路對預估晶圓級封裝焊點可靠度影響研究," 碩士, 動力機械工程學系, 國立清華大學, 新竹市, 2021. [Online]. Available: https://hdl.handle.net/11296/723fjy
[43] Q.-H. Su and K.-N. Chiang, "Predicting Wafer-Level Package Reliability Life Using Mixed Supervised and Unsupervised Machine Learning Algorithms," Materials, vol. 15, no. 11, p. 3897, 2022.
[44] 蘇清華, "數據分布於核嶺回歸模型對晶圓級封裝之可靠度預估研究," 碩士, 動力機械工程學系, 國立清華大學, 新竹市, 2022. [Online]. Available: https://hdl.handle.net/11296/h9vg89
[45] G. R. Huang, M. Y. Chen, and K. N. Chiang, "Prediction of Fan-Out Level Packaging Warpage using PSO-based Modified Convolutional Neural Network model with Laplacian Filter," 2021 International Conference on Electronics Packaging (ICEP), pp. 101-102, 2021.
[46] 黃冠儒, "以粒子群最佳化法決定神經網路之初始權重於預估面板級封裝之翹曲研究," 碩士, 動力機械工程學系, 國立清華大學, 新竹市, 2021. [Online]. Available: https://hdl.handle.net/11296/962p8b
[47] S. Liu, S. Panigrahy, and K. Chiang, "Prediction of fan-out panel level warpage using neural network model with edge detection enhancement," in 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), 2020: IEEE, pp. 1626-1631.
[48] 王柏盛, "面板級封裝非對稱翹曲研究及使用極限隨機樹演算法預測翹曲幾何," 碩士, 動力機械工程學系, 國立清華大學, 新竹市, 2022. [Online]. Available: https://hdl.handle.net/11296/qh3d35
[49] C. Chang, C. Lee, and K. Chiang, "Using Grid Search Methods and Parallel Computing to Reduce AI Training Time for Reliability Lifetime Prediction of Wafer-Level Packaging," in 2023 24th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), 2023: IEEE, pp. 1-5.
[50] K. J. Bathe, "Finite element method," Wiley encyclopedia of computer science and engineering, pp. 1-12, 2007.
[51] Z. Guo, S. You, X. Wan, and N. Bićanić, "A FEM-based direct method for material reconstruction inverse problem in soft tissue elastography," Computers & structures, vol. 88, no. 23-24, pp. 1459-1468, 2010.
[52] H. Chang, B. Chen, and K. Chiang, "The effect of data distribution in Ensemble Learning Algorithms on WLCSP reliability Prediction," in 2021 16th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2021: IEEE, pp. 60-63.
[53] T. Blecha and J. Pihera, "Epoxy resin curing process evaluation based on signal frequency analysis from interdigital structure sensor," in 3rd Electronics System Integration Technology Conference ESTC, 2010: IEEE, pp. 1-4.
[54] S.-J. Hwang and Y.-S. Chang, "PVTC equation for epoxy molding compound," IEEE Transactions on components and packaging technologies, vol. 29, no. 1, pp. 112-117, 2006.
[55] D. Roylance, "Engineering viscoelasticity," Department of Materials Science and Engineering–Massachusetts Institute of Technology, Cambridge MA, vol. 2139, pp. 1-37, 2001.
[56] N. Srikanth, "Warpage analysis of epoxy molded packages using viscoelastic based model," Journal of materials science, vol. 41, no. 12, pp. 3773-3780, 2006.
[57] C. Zhu, P. Guo, and Z. Dai, "Investigation on wafer warpage evolution and wafer asymmetric deformation in fan-out wafer level packaging processes," in 2017 18th International Conference on Electronic Packaging Technology (ICEPT), 2017: IEEE, pp. 664-668.
[58] 陳柏伸, "使用KNN結合聚類分析對晶圓級封裝之可靠度預估研究," 碩士, 動力機械工程學系, 國立清華大學, 新竹市, 2022. [Online]. Available: https://hdl.handle.net/11296/a9789p
[59] Z. Shu, B. Wang, and K. Chiang, "Using Extra Trees Machine Learning Algorithm to Predict the Asymmetric Warpage Geometry of Panel Level Packaging," in 2022 17th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2022: IEEE, pp. 1-4.
[60] H. Chen, B. Chen, and K. Chiang, "Predict the Reliability Life of Wafer Level Packaging using K-Nearest Neighbors algorithm with Cluster Analysis," in 2022 17th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2022: IEEE, pp. 1-5.
[61] M. Su et al., "Warpage simulation and experimental verification for 320 mm× 320 mm panel level fan-out packaging based on die-first process," Microelectronics Reliability, vol. 83, pp. 29-38, 2018.
[62] T. Braun et al., "Panel Level Packaging-A view along the process chain," in 2018 IEEE 68th Electronic Components and Technology Conference (ECTC), 2018: IEEE, pp. 70-78.
[63] H. Chen and K. Chiang, "The Effect of Geometric and Material Uncertainty on Debonding Warpage in Fan-Out Panel Level Packaging," in 2023 24th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), 2023: IEEE, pp. 1-6.