隨著現今科技的日新月異，我們的生活已經與半導體產品緊密相連，特別是電晶體和記憶體元件，它們是半導體產品中最基礎的組成部分。各類半導體產品強調高效能、低功耗及縮小尺寸等訴求，然而隨著摩爾定律的演進，在微縮的過程中，我們經常會面臨製程技術上的困難，包括低熱預算的問題以及元件前後段垂直整合的挑戰，這些連續而來的問題是我們所必須克服的。
基於上述這些想法，本篇研究我們使用低溫綠光奈秒雷射結晶非晶矽以及低溫微波退火製程來進行摻雜活化及鐵電層結晶，這兩項技術可以有效降低的熱預算，並有機會實現在單晶片上的三維積體電路整合。另外，電晶體的閘極氧化層選用超晶格氧化鉿鋯，該材料的鐵電性質產生的負電容效應有望打破物理的極限，得到較低的次臨界擺幅。由相同材料製造的鐵電電晶體非揮發性記憶體，相較於傳統的記憶體，擁有更低的功耗以及更高的操作速度，有機會實現記憶體內的運算，突破馮·紐曼架構的框架。
本篇研究將被分成兩部分，我們以電容匹配模型作為理論基礎，分別製作適用於邏輯元件和記憶體元件的鐵電電晶體。
第一部分為鐵電薄膜電晶體。元件製作於絕緣層上覆非晶矽基板，經由綠光奈秒雷射掃描，將非晶矽薄膜結晶成複晶矽。隨後電子束微影進行主動區的定義，再利用非等向性蝕刻形成薄膜的結構，此薄膜結構可稍微節省一些熱預算。接著，透過原子層沉積得到12 nm之超晶格氧化鉿鋯氧化層，並以氮化鈦作為閘極金屬。量測的結果得到次臨界擺幅最小來到75 mV/dec，其Ion/Ioff的比值有不錯的1.6 × 106，對於DIBL及GIDL漏電流都有著良好的抑制能力。
第二部分為鐵電薄膜電晶體非揮發性記憶體。此元件與前者有著相同的製程，其中值得一提的是，我們使用SiO2作為介面層來改善通道與氧化層之間的介面品質，以及12 nm的超晶格氧化鉿擁有較低的缺陷密度，藉由這兩者提升記憶窗口。鐵電電晶體非揮發性記憶體在 ± 4 V直流正反掃量測時，萃取出最大1.21 V的記憶窗口；而透過脈衝量測，施加 ± 5 V, 100 ns的脈衝進行寫入/抹除操作，此方法量測到之記憶窗口為1.26 V，相較於直流正反掃略大一點。其耐用度達到103cycle，耐久度可達104秒以上並保持極佳的特性。
無論是用於邏輯元件或非揮發性記憶體元件，鐵電電晶體都展現出不錯的性能，再加上它與現今的CMOS製程相容的特點，使其在未來半導體產業的應用上具有巨大的發展潛力。

With the advancement of today's technology, our lives are closely connected with semiconductor products, especially transistors and memory devices, which are the most fundamental components of semiconductor products. Semiconductor products emphasize high performance, low power consumption, and reduced size. However, with the evolution of Moore's Law, in the process of shrinking, we are often confronted with process technology difficulties, including the problem of low thermal budgets and the challenge of vertically integrating the front end and back end of the device, which are consecutive problems that we have to overcome.
Based on these ideas, in this study, we use low-temperature green nanosecond laser to crystallize amorphous silicon into polycrystalline silicon and a low-temperature microwave annealing process for dopant activation and ferroelectric layer crystallization, which can effectively reduce the thermal budget and potentially enable three-dimensional integrated circuit integration on a single chip. In addition, the gate oxide layer of the ferroelectric thin-film-transistor (FeTFT) is made of superlattice HfO2-ZrO2 (SLHZO), whose ferroelectricity produces a negative capacitance effect that is expected to break the physical limit and result in lower subthreshold swing (SS). The ferroelectric thin-film-transistor Non-volatile Memory (FeTFT NVM) made of the same material has lower power consumption and higher operating speed than the conventional memory, and it has the opportunity to realize in-memory computing and break through the framework of the Von Neumann architecture.
This research will be divided into two parts, in which we use the capacitance matching model as the theoretical basis to fabricate ferroelectric transistors for logic devices and memory devices, respectively.
The first part is a FeTFT. The device is fabricated on an amorphous silicon substrate covered with an insulating layer, and the amorphous silicon film is crystallized into polycrystalline silicon by green nanosecond laser scanning. Subsequently, the active region is defined by electron beam lithography, and a thin film structure is formed by anisotropic etching, which saves some thermal budget. Next, a 12 nm SLHZO layer was obtained by atomic layer deposition, and titanium nitride was used as the gate metal. The measurement results show that the subthreshold swing is minimized to 75 mV/dec, and the Ion/Ioff ratio is 1.6 × 106, which is suitable for DIBL and GIDL leakage current suppression.
The second part is a FeTFT NVM. This device has the same process as the previous one, and it is worth mentioning that we use SiO2 as the interfacial layer to improve the interface quality between the channel and the oxide layer, and the 12 nm SLHZO has a lower defect density, which enhances the memory window. FeTFT NVM extracted a maximum memory window of 1.21 V during ± 4 V DC forward/backward sweep measurements, while the memory window measured by pulse measurement, applying ± 5 V, 100 ns pulse for write/erase operations, was 1.26 V, which is slightly larger than that of DC forward/backward sweep. The durability reaches 103 cycles and the endurance reaches 104 seconds or more and maintains excellent characteristics.
FeTFT shows excellent performance in logic or non-volatile memory devices, and their compatibility with today's CMOS processes makes them great potential for future semiconductor industry applications.

目錄
摘要 i
Abstract iii
致謝 vi
目錄 vii
圖目錄 x
表目錄 xii
第一章 1
緒論 1
1.1 電晶體的演進及挑戰 (Scaling of Transistor) 1
1.2 二氧化鉿基的鐵電材料 (HfO2-based ferroelectric material) 5
1.3 超晶格氧化鉿鋯鐵電電容 (HfO2-ZrO2 Superlattice Ferroeletric Capacitor) 8
1.4 鐵電電晶體非揮發記憶體 (Ferroelectric Field-Effect-Transistor Non-Volatile Memory) 10
1.5 低熱預算之製程技術 (Low Thermal Budget process technology) 12
1.5.1 綠光奈秒脈衝雷射結晶 (Green Nanosecond-Pulse Laser Crystallization) 12
1.5.2 微波退火 (Microwave Annealing) 14
第二章 16
機制探討 16
2.1 負電容效應 (Negative capacitance effect) 16
2.2 Landau-Khalatnikov (L-K) Equation Model 18
2.3 遲滯現象的機制 (Mechanism of Hysteresis) 20
2.3.1 鐵電氧化層厚度 (Thickness of FE oxide) 20
2.3.2 電容匹配 (Capacitance Matching) 21
2.4 電荷捕捉 (Charge Trapping) 24
2.5 介面層 (Interfacial Layer) 26
2.6 讀取操作之影響 (Impact of Read Operation) 28
第三章 32
鐵電薄膜電晶體 32
3.1 實驗動機 (Motivation) 32
3.2 製程步驟 (Device Fabrication) 33
3.3 穿透式電子顯微鏡與能量散射x光能譜分析 (TEM, and EDS Analysis) 38
3.4 電晶體電特性分析 (Electric Characteristics Analysis) 41
第四章 46
鐵電薄膜電晶體非揮發性記憶體 46
4.1 實驗動機 (Motivation) 46
4.2 製程步驟 (Device Fabrication) 48
4.3 記憶體電特性之分析 (Memory Window and Switching Speed Analysis) 51
4.4 可靠度分析 (Reliability Analysis) 55
第五章 59
結論與未來展望 59
5.1 結論 (Conclusion) 59
5.2 未來展望 (Future Work) 60
參考文獻 61

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第二章
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第三章
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第四章
[4-1] H. Mulaosmanovic, J. Ocker, S. Müller, M. Noack, J. Müller, P. Polakowski, T. Mikolajick, and S. Slesazeck, “Novel ferroelectric FET based synapse for neuromorphic systems,” 2017 Symposium on VLSI Technology, 2017, pp. T176-T177, doi: 10.23919/VLSIT.2017.7998165.
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