鍺具有較高的電子及電洞遷移率，製程與傳統矽元件高度相容，使用鍺取代矽作為通道材料，在高度要求元件運算速度的背景下，已成為重要研究方向。然而，氧化鍺作為通道與高介電層間的界面層，其穩定性遠不如二氧化矽，容易降解外，缺陷密度也高，導致閘極漏電流高、閘極電容特性差等諸多問題，因此，尋找其他合適材料作為鍺元件之界面層，成為重要研究方向。其中，氧化釔具有氧化物穩定性極佳的特點，不易降解，有利於降低界面層之界面缺陷密度，則合適的厚度下，合適的厚度下，也有利於抑制氧化鍺生成，達到提升閘極電容特性之目的，本研究亦針對使用氧化釔作為界面層特性進行深入探討。
第一部分，改變氧化釔界面層厚度、電漿製程參數，找出氧化釔沉積之最佳工程參數。氧化釔具有氧化物穩定性極佳的特點，不易降解，有利於降低界面層之界面缺陷密度，則合適的厚度下，也有利於抑制氧化鍺生成，達到提升閘極電容特性之目的。於Ge MOS device成功利用氧化釔界面層，得到超薄等效厚度，並具有極小之缺陷密度，以及近乎為零之遲滯特性，並成功利用氧電漿修復工程降低border charge及漏電流。
第二部分將氧化釔與其他材料界面層進行比對，包含氮化鉿、氧化鍺及氧化鋁，應用於Ge MOS device進行探討與比較。雖然具有氧化釔界面層Ge MOS device的漏電流特性較氮化鉿差，但其擁有相對更小之界面缺陷，以及近乎為零之遲滯，說明其作為界面層仍具潛力。
第三部分透過閘堆疊工程，改善先進電晶體特性。實驗一利用雙層高介電閘極氧化物，改變介電層結晶特性，並降低閘極漏電流、關閉電流、關閉功耗。實驗二利用氫退火修復界面缺陷，但對於電晶體特性改善不大。實驗三利用閘金屬中增加鈦金屬層，形成富鈦閘金屬，成功降低閘極漏電流，但對於閘極電容、次臨界擺幅特性改善不大。

Because germanium (Ge) has a higher electron and hole mobility and is highly compatible with fabrication processes of silicon CMOS devices, Ge channel an important research topic for high speed IC applications. However, the thermal stability of germanium oxide interface layer between the channel and high-k gate dielectric is poorer than that of silicon dioxide one. The thermal stability problem causes high defect density, leading to issues such as high leakage current, and low capacitance density in gate stack, and other problems. Therefore, alternative interfacial layer of Ge MOS devices is very desirable and has become an important task. Yttrium oxide, with excellent thermal stability, is advantageous in reducing the defect density of the interface layer. In this thesis, yttrium oxide interfacial layer for Ge MOS devices was studied.
In the first part, effects of thickness of the yttrium oxide interface layer and plasma processing parameters were studied to form yttrium oxide. A Y2O3 with suitable thickness, also helps inhibit the formation of germanium suboxide and increase the capacitance density of gate stack in Ge MOS device.An ultra-thin equivalent oxide thickness, low interface trap density, and nearly no hysteresis in Ge MOS device are achieved by using a Y2O3 interface layer. A plasma treatment on Y2O3 was also used to reduce border trap charge and gate leakage current.
In the second part, interfacial layers of yttrium oxide, hafnium nitride, germanium oxide, and aluminum oxide in Ge MOS device were investigated and compared. Although the gate leakage current of Ge MOS device with yttrium oxide is higher than that with hafnium nitride, the former device with low interface trap and nearly zero hysteresis indicates its potential as an interfacial layer.
The third part focuses on enhancing the characteristics of advanced transistors through gate stack process. In Experiment 1, a double-layer high-k was employed to alter the crystalline properties of the dielectric layer, resulting in reduced gate leakage current, off-current, and standby power. In Experiment 2, hydrogen annealing is used to treat interface defects, but the improvement in transistor characteristics was limited. In Experiment 3, the addition of a titanium layer to the gate metal formed a titanium-rich gate metal, successfully reducing gate leakage current. However, the improvement in gate capacitance and subthreshold swing characteristics was not significant.

第一章 序論 P16
1.1 前言 P16
1.2 鍺作為通道材料之優缺點 P17
1.3 閘極氧化層與界面層之選擇 P17
1.4 氧化釔之特性研究 P18
1.5 先進製程之閘極氧化物選擇 P19
1.6 氫退火 P20
1.7 氮化鈦閘極金屬層效應 P20
1.8 論文架構 P21
第二章 元件製程與量測 P26
2.1 氧化釔電容片製作方式 P26
2.2 不同金屬界面層電容片製作方式 P26
2.3 電性量測 P27
2.3.1 兩點量測電容－電壓曲線 P28
2.3.2 遲滯特性量測 P28
2.3.3 兩點量測電流－電壓曲線 P29
2.3.4 可靠度量測 P29
2.4 先進鰭式電晶體標準製程 P29
2.5 鰭式電晶體電性量測 P30
第三章 製程條件對於氧化釔界面層電容片之影響 P31
3.1 研究動機 P31
3.2 氧化釔界面層電容片製程步驟 P33
3.3 電性量測 P34
3.4 結果與討論 P34
3.4.1 氧化釔電漿修復時間對電容之影響 P34
3.4.2 氧化釔厚度對電容特性之影響 P35
3.4.3 界面層後對火與介電層後退火對P型基板電容電容特性之影響 P36
3.4.4 界面層後對火與介電層後退火對N型基板電容特性之影響 P38
3.4.5 使用氧電漿原子層沉積之電容片特性 P39
3.5 結論 P39
第四章 不同界面層對鍺電容片特性比較 P63
4.1 研究動機 P63
4.2 製程與量測 P65
4.3 結果與討論 P66
4.3.1 不同界面層鍺P型基板電容片之電容及漏電特性 P66
4.3.2 不同介面層鍺N型基板電容片之電容及漏電特性 P68
4.4 結論 P69
第五章 閘極工程對先進CMOS元件電特性之影響 P85
5.1 HK堆疊對先進CMOS元件特性之影響 P86
5.1.1 研究動機 P86
5.1.2 元件製程與量測 P87
5.1.3 結果與討論 P87
5.1.4 結論 P89
5.2 氫退火對先進CMOS元件之影響 P98
5.2.1 研究動機 P98
5.2.2 元件製程與量測 P98
5.2.3 結果與討論 P99
5.2.4 結論 P100
5.3 鈦金屬層對於先進CMOS元件特性之影響 P108
5.3.1 研究動機 P108
5.3.2 元件製程與量測 P108
5.3.3 結果與討論 P109
5.3.4 結論 P110
第六章 結論與未來展望 P120
6.1 結論 P120
6.2 未來展望 P121
第七章 參考文獻 P122

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