本篇研究使用具鐵電性質的氧化鉿鋯薄膜(HZO)作為閘極介電層的材料，並以超晶格矽/矽鍺堆疊作為通道。由於鐵電材料的自發性極化現象所產生的負電容效應將有望於突破傳統電晶體的次臨界擺幅之物理極限，而氧化鉿鋯除了具有在低膜厚下展現出高鐵電性之特性外，其材料本身也具有高介電常數，能夠提高驅動電流、降低閘極漏電流。並且使用矽/矽鍺超晶格堆疊通道，藉由應變矽技術、高品質超晶格磊晶通道和高遷移率材料，將進一步提升電晶體之驅動電流，此垂直之堆疊通道以及Ω閘極電晶體，以上皆更利於應用於未來電晶體尺寸之微縮。
第一部分為金屬-絕緣層-半導體結構之電容，其絕緣層分別以氧化鉿鋯及二氧化鉿作為比較，比較在不同退火溫度下所展現出的電性。於退火溫度550°C下、退火30秒時，將展現出最佳之鐵電特性，具有最高之殘餘極化量、最大的記憶窗口，並克服更低溫下絕緣層結晶性不佳，及矽鍺層在更高溫下擴散的問題。
第二部分為鐵電矽/矽鍺堆疊之Ω閘極電晶體之研究。分別以氧化鉿鋯和二氧化鉿，應用在矽/矽鍺堆疊之Ω閘極電晶體的閘極氧化層上，以作為有無具鐵電性質之比較，發現具有鐵電性之閘極氧化層的電晶體，將會有更高的開關電流比為1.97×107、更低的平均次臨界擺幅71.1 mV/dec。除此之外，也分別以N, P型的鐵電矽/矽鍺堆疊之Ω閘極電晶體，模擬CMOS(互補式金屬氧化物半導體)反相器測量VTC曲線和電壓增益，可以發現其良好的反相器特性曲線，及極佳的電壓增益值111.4 (V/V)，這歸因於N, P型的鐵電矽/矽鍺堆疊之Ω閘極電晶體有對稱的臨界電壓。
以上結果證實，將鐵電材料應用在矽/矽鍺堆疊之Omega閘極電晶體的閘極氧化層上，將會大幅提高開關電流比、降低次臨界擺幅，展現出極出色的表現，加上良好的反相器特性以及二氧化鉿基材料與現今CMOS製程極高的相容性，使其對於在未來超低功耗電路應用上具有相當高的潛力。

In this study, a ferroelectric Hf0.5Zr0.5O2 thin film was used as the gate dielectric layer, and a superlattice Si/ Si0.8Ge0.2 stack was used as the channel. The negative capacitance effect generated by the spontaneous polarization phenomenon of the ferroelectric material is expected to break through the physical limit of the subthreshold swing of traditional transistors. In addition to exhibiting high ferroelectric properties at low film thickness, Hf0.5Zr0.5O2 also has a high dielectric constant, which can increase the drive current and reduce gate leakage current. Furthermore, the use of a Si/ Si0.8Ge0.2 superlattice stack channel, through strain engineering, high-quality superlattice epitaxial channels, and high-mobility materials, will further enhance the transistor's drive current. The vertical stack channel and Omega gate transistor are also more suitable for application in the future shrinking of transistor size.
In the first part, the capacitor structure of metal-insulator-semiconductor with Hf0.5Zr0.5O2 and HfO2 as insulator layers is compared in terms of electrical properties exhibited under different annealing temperatures. It is found that annealing at 550°C for 30 seconds exhibits the best ferroelectric characteristics, with the highest remanent polarization, the largest memory window, and overcoming the poor crystallinity of the insulating layer at lower temperatures and the diffusion of silicon-germanium layer at higher temperatures.
The second part studies the Ω-gate transistor of ferroelectric Si/ Si0.8Ge0.2 stack. Hf0.5Zr0.5O2 and HfO2 are respectively applied to the gate oxide layer of omega-gate transistors in Si/ Si0.8Ge0.2 stack for comparison of ferroelectric properties. It is found that transistors with ferroelectric gate oxide layer have a higher ION/IOFF of 1.97×107 and a lower average S.S. of 71.1 mV/dec. In addition, N and P-type ferroelectric Si/ Si0.8Ge0.2 stack omega-gate transistors are respectively simulated for measuring the inverter voltage transfer characteristic of the CMOS inverter and voltage gain The good inverter characteristic curve and excellent voltage gain value of 111.4 (V/V) are attributed to the symmetrical threshold voltage of n and P-type ferroelectric Si/ Si0.8Ge0.2 stack omega-gate transistors.
The above results confirm that applying ferroelectric materials to the gate oxide layer of Si/ Si0.8Ge0.2 stacked omega gate transistors can significantly increase ION/IOFF, reduce subthreshold swing, and exhibit outstanding performance. In addition, the good inverter characteristics and the excellent compatibility of the hafnium dioxide substrate with current CMOS processes make it highly potential for future ultra-low power circuit applications.

摘要 iii
Abstract v
致謝 vii
目錄 viii
圖目錄 x
第一章 緒論 1
1.1 摩爾定律 (Moore's law) 1
1.2 Ω閘極電晶體 (Omega-gate Field-Effect-Transistor) 4
1.3 高載子遷移率通道 (High mobility channel material) 5
1.4 矽鍺/矽堆疊通道(Stack Silicon-Germanium/ Si channel) 7
1.5 鐵電二氧化鉿基材料(Ferroelectric HfO2 based material) 10
1.6 實驗動機 (Motivation) 15
1.7 論文架構 (Paper Organization) 19
第二章 機制探討 21
2.1 應變矽原理 (Principle of Strained Silicon) 21
2.2 鐵電特性 (Ferroelectric properties) 26
2.3 負電容現象 (Negative capacitance effect) 30
第三章 鐵電氧化鉿鋯應用於矽/矽鍺堆疊之MIS電容 33
3.1 製程步驟 (Device Fabrication) 33
3.2 材料分析 (Material Analysis) 37
3.3 電性分析 (Electric Characteristics Analysis) 41
第四章 鐵電氧化鉿鋯應用於矽/矽鍺堆疊之Ω閘極電晶體及反相器 45
4.1 製程步驟 (Device Fabrication) 45
4.2 材料分析 (Material Analysis) 49
4.3 電性分析 (Electric Characteristics Analysis) 50
4.4 TCAD模擬矽鍺/矽堆疊鰭式電晶體 (TCAD Simulation of SiGe/ Si SL FinFET) 56
第五章 結論 61
參考文獻 62

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