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作者(中文):楊青如
作者(外文):Yang, Ching-Ru
論文名稱(中文):高性能P型與N型矽鍺/矽應變超晶格鰭式場效電晶體及反相器之研究
論文名稱(外文):Study of High Performance P- and N-type SiGe/Si Strained Super-Lattice-FinFET and Inverter
指導教授(中文):吳永俊
指導教授(外文):Wu, Yung-Chun
口試委員(中文):朱鵬維
羅廣禮
口試委員(外文):Chu, Peng-Wei
Luo, Guang-Li
學位類別:碩士
校院名稱:國立清華大學
系所名稱:工程與系統科學系
學號:110011544
出版年(民國):112
畢業學年度:111
語文別:中文
論文頁數:72
中文關鍵詞:超晶格應力矽鍺鰭式場效電晶體反相器
外文關鍵詞:super-latticestrainSiGeFinFETinverter
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半導體在現代科技中扮演著關鍵的角色,更是和人類生活密不可分,然而隨著摩爾定律的演進,元件尺寸微縮發展逐漸遇到瓶頸,當前應用廣泛的FinFET技術在物理及電性上達到極限,因此如何在此前提下提升電晶體的特性成為一大挑戰。當前有許多研究提出新穎的解決方案,例如使用HKMG(High-K Metal-Gate)、應用高遷移率材料於電晶體通道當中,或是利用應變技術有效提升載子遷移率,以期提高半導體元件性能。
基於上述,本研究使用高遷移率材料SiGe與傳統材料Si進行週期性磊晶,製作具前瞻性的高性能P型與N型Si0.8Ge0.2/Si超晶格(Super-Lattice, SL)異質通道應用於FinFET結構,利用兩者材料間的晶格常數差異產生應變效應,再結合材料特性,有效提高通道載子遷移率與驅動電流,在達到提升電晶體元件特性的同時延伸摩爾定律的發展。
本研究首先進行不同電晶體通道材料包括主軸之Si0.8Ge0.2/Si應變超晶格異質磊晶、傳統Si及Si0.8Ge0.2的比較,以微區繞射(Nano Beam Diffraction, NBD)、拉曼光譜(Raman spectra)、X光倒易空間圖譜(XRD reciprocal space mapping, XRD RSM )之材料分析對Si0.8Ge0.2/Si應變超晶格鰭式場效電晶體的應變效應進行分析與證明,而電特性的部分之次臨界擺幅值最小降至88 mV/dec,其ION/IOFF最高達到9.47×105,並且Gm,max也獲得375.2 μS/μm之結果,證明Si0.8Ge0.2/Si應變超晶格異質磊晶結構的優勢。
接著提出擁有更低之鰭片高度且膜厚分佈均勻的周期性堆疊Si0.8Ge0.2/Si Super-Lattice異質磊晶結構,在後續加上金屬化製程,以深入探討其反相器之特性,在電性的部分之ION/IOFF優化至1.35×106,並且得到更高的驅動電流。後續也用Sentaurus TCAD 模擬電晶體應用至反相器及靜態隨機存取記憶體(Static Random-Access Memory, SRAM)的特性,得到相當良好的成果。
本研究通過Si0.8Ge0.2/Si應變超晶格異質磊晶結構與其他通道材料之電晶體比較和延伸探討Si0.8Ge0.2/Si應變超晶格鰭式場效電晶體及反相器驗證了其出色的性能,並展示了在未來半導體領域的應用潛力,更為未來高遷移率應變通道及其應用提供了一個新的方向。
Semiconductors play a critical role in modern technology and are closely intertwined with human life. However, with the evolution of Moore's Law, the device scaling has gradually reached a bottleneck. The current widely used FinFET technology has reached its physical and electrical limits. Therefore, optimizing the transistor characteristics under these circumstances becomes a major challenge. Currently, many researches have proposed novel solutions, such as using HKMG, applying high-mobility materials in transistor channels, or using stress technology to effectively increase carrier mobility, to improve the performance of semiconductor devices.
Based on the above, this study uses high-mobility material SiGe and traditional material Si for periodic epitaxy to fabricate prospective high-performance P-type and N-type Si0.8Ge0.2/Si SL heterogeneous channels for application in the FinFET structure. By utilizing the difference in lattice constant between the two materials to generate strain effects, combined with the material properties, effectively improves the channel carrier mobility and drive current, and extends the development of Moore's Law while improving the characteristics of transistor devices.
First, different transistor channel materials including Si0.8Ge0.2/Si strain SL heterogeneous epitaxy of the main axis, conventional Si and Si0.8Ge0.2 were compared in this study. The strain effect of Si0.8Ge0.2/Si strained SL FinFET was analyzed and demonstrated by NBD, Raman spectra, and XRD RSM. As for the electrical characteristics, the minimum subthreshold swing value drops to 88 mV/dec, and its ION/IOFF reaches a maximum of 9.47×105, and Gm,max also achieves 375.2 μS/μm, which demonstrates the advantage of Si0.8Ge0.2/Si strained SL heterogeneous epitaxy structure.Subsequently, a periodic stacked Si0.8Ge0.2/Si SL heterogeneous epitaxy structure with lower Fin height and uniform film thickness distribution was proposed. Metallization processes were applied to further investigate the characteristics of inverters. In terms of electrical performance, the ION/IOFF ratio was optimized to 1.35×106, and higher drive currents were achieved. Moreover, Sentaurus TCAD simulations were used to simulate the transistor application in inverters and SRAM, yielding excellent results.
In summary, this study compared Si0.8Ge0.2/Si strained SL heterogeneous epitaxy structure with other channel materials and extended the discussion on Si0.8Ge0.2/Si strained SL FinFET and inverters, verifying their outstanding performance and demonstrating the potential in the future semiconductor area. Also provides a new direction for future high-mobility strain channel research and its applications.
中文摘要------------------------i
Abstract------------------------iii
致謝------------------------v
目錄------------------------vi
表目錄------------------------viii
圖目錄------------------------ix
第一章 簡介------------------------1
1.1 摩爾定律(Moore’s Law)------------------------1
1.2 高載子遷移率之通道材料------------------------4
1.3 應變工程技術------------------------5
1.3.1 應變矽之應用------------------------5
1.3.2 應變矽鍺之應用------------------------8
1.4 超晶格(Super-Lattice, SL)磊晶結構------------------------10
1.5 研究動機------------------------16
1.6 論文架構------------------------20
第二章 理論基礎------------------------22
2.1 MOSFET與CMOS Inverter操作機制------------------------22
2.1.1 MOSFET------------------------22
2.1.2 CMOS Inverter------------------------24
2.2 電晶體重要參數------------------------26
2.2.1 臨界電壓------------------------26
2.2.2 次臨界擺幅(Subthreshold Swing)------------------------27
2.2.3 汲極引發位能障降低------------------------28
2.3 載子遷移率------------------------29
2.4 材料分析概述------------------------31
2.4.1 拉曼光譜(Raman spectra)------------------------31
2.4.2 X光倒易空間圖譜(X-ray Reciprocal Space Mapping, RSM)-----------33
第三章 不同通道材料之電晶體比較------------------------35
3.1 製程步驟------------------------35
3.2 矽鍺/矽應變超晶格鰭式場效電晶體材料分析------------------------38
3.3 電晶體電性分析------------------------45
第四章 矽鍺/矽應變超晶格鰭式場效電晶體及反相器------------------------51
4.1 製程步驟------------------------51
4.2 矽鍺/矽應變超晶格鰭式場效電晶體材料分析------------------------55
4.3 電晶體電性分析------------------------57
4.4 矽鍺/矽應變超晶格鰭式場效電晶體TCAD模擬分析------------------------61
第五章 結論------------------------67
參考文獻------------------------69
[1] "International Roadmap for Devices and Systems (IRDS™) 2022 Edition." https://irds.ieee.org/editions/2022/executive-summary (accessed 2023).
[2] D. Hisamoto et al., "FinFET-a self-aligned double-gate MOSFET scalable to 20 nm," IEEE Transactions on Electron Devices, vol. 47, no. 12, pp. 2320-2325, 2000, doi: 10.1109/16.887014.
[3] "International Roadmap for Devices and Systems (IRDS™) 2020 Edition." https://irds.ieee.org/editions/2020/more-moore (accessed 2023).
[4] K. J. Kuhn, A. Murthy, R. Kotlyar, and M. Kuhn, "(Invited) Past, Present and Future: SiGe and CMOS Transistor Scaling," ECS Transactions, vol. 33, no. 6, p. 3, 2010/10/01 2010, doi: 10.1149/1.3487530.
[5] J. Welser, J. L. Hoyt, S. Takagi, and J. F. Gibbons, "Strain dependence of the performance enhancement in strained-Si n-MOSFETs," in Proceedings of 1994 IEEE International Electron Devices Meeting, 11-14 Dec. 1994 1994, pp. 373-376, doi: 10.1109/IEDM.1994.383389.
[6] K. Rim et al., "Strained Si NMOSFETs for high performance CMOS technology," in 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184), 12-14 June 2001 2001, pp. 59-60, doi: 10.1109/VLSIT.2001.934946.
[7] A. Agrawal et al., "Gate-All-Around Strained Si0.4Ge0.6 Nanosheet PMOS on Strain Relaxed Buffer for High Performance Low Power Logic Application," presented at the 2020 IEEE International Electron Devices Meeting (IEDM), 2020.
[8] E. S. Cor Claeys, Ed. Germanium-Based Technologies From Materials to Devices, 1st ed. (Chapter 11. Advanced Germanium MOS Devices (C. On Chui, K.C. Saraswat).). (in English), p. 480.
[9] K. Ismail, J. O. Chu, and B. S. Meyerson, "High hole mobility in SiGe alloys for device applications," Applied Physics Letters, vol. 64, no. 23, pp. 3124-3126, 1994, doi: 10.1063/1.111367.
[10] M. V. Fischetti and S. E. Laux, "Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys," Journal of Applied Physics, vol. 80, no. 4, pp. 2234-2252, 1996, doi: 10.1063/1.363052.
[11] G. Hellings et al., "Si/SiGe superlattice I/O finFETs in a vertically-stacked Gate-All-Around horizontal Nanowire Technology," in 2018 IEEE Symposium on VLSI Technology, 18-22 June 2018 2018, pp. 85-86, doi: 10.1109/VLSIT.2018.8510654.
[12] Y.-L. Li et al., "Improved Electrical Characteristics of Bulk FinFETs With SiGe Super-Lattice-Like Buried Channel," IEEE Electron Device Letters, vol. 40, no. 2, pp. 181-184, 2019, doi: 10.1109/led.2018.2890535.
[13] N. Loubet et al., "Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET," in 2017 Symposium on VLSI Technology, 5-8 June 2017 2017, pp. T230-T231, doi: 10.23919/VLSIT.2017.7998183.
[14] S. M. Sze and M.-K. Lee, Semiconductor Devices: Physics and Technology, 3rd ed. 2016.
[15] TCAD Sentaurus Device, Synopsys SDevice Ver.J-2014.09. Synopsys, Inc., Mountain View, CA, USA.
[16] A. Es-Sakhi and M. H. Chowdhury, "Analytical model to estimate the subthreshold swing of SOI FinFET," in 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS), 8-11 Dec. 2013 2013, pp. 52-55, doi: 10.1109/ICECS.2013.6815343.
[17] D. A. Neamen, Semiconductor Physics and Devices: Basic Principles. McGraw-Hill, 2012.
[18] Y. Min et al., "Hybrid-orientation technology (HOT): opportunities and challenges," IEEE Transactions on Electron Devices, vol. 53, no. 5, pp. 965-978, 2006, doi: 10.1109/TED.2006.872693.
[19] G. Wang, Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond Springer, 2019.
[20] S. A. Mala, L. Tsybeskov, D. J. Lockwood, X. Wu, and J. M. Baribeau, "Raman scattering in Si/SiGe nanostructures: Revealing chemical composition, strain, intermixing, and heat dissipation," Journal of Applied Physics, vol. 116, no. 1, 2014, doi: 10.1063/1.4886598.
[21] M.-H. Cheng, Strain Studies of Silicon-Germanium Hetero-Epitaxial Layer by X-ray Reciprocal Space Mapping. 2007.
[22] M. Wormington et al., "Asymmetric Relaxation of SiGe in Patterned Si Line Structures," AIP Conference Proceedings, vol. 931, no. 1, pp. 220-225, 2007, doi: 10.1063/1.2799374.
[23] K. Cheng et al., "High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET," in 2012 International Electron Devices Meeting, 10-13 Dec. 2012 2012, pp. 18.1.1-18.1.4, doi: 10.1109/IEDM.2012.6479063.
[24] "Chapter 2 - Strain, stability, reliability and growth," in Semiconductors and Semimetals, vol. 74, S. C. Jain and M. Willander Eds.: Elsevier, 2003, pp. 9-40.
[25] K. Shahzad, D. J. Olego, and D. A. Cammack, "Thickness dependence of strains in strained‐layer superlattices," Applied Physics Letters, vol. 52, no. 17, pp. 1416-1418, 1988, doi: 10.1063/1.99133.
[26] R. P. G. Karunasiri and K. L. Wang, "Quantum devices using SiGe/Si heterostructures," Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena, vol. 9, no. 4, pp. 2064-2071, 1991, doi: 10.1116/1.585778.
[27] K. Arimoto et al., "Hole mobility enhancement observed in (110)-oriented strained Si," Japanese Journal of Applied Physics, vol. 59, no. SG, p. SGGK06, 2020/02/07 2020, doi: 10.7567/1347-4065/ab6591.
[28] W. T. Chang, M. H. Li, C. H. Hsu, W. C. Lin, and W. K. Yeh, "Modifying Threshold Voltages to n- and p- Type FinFETs by Work Function Metal Stacks," IEEE Open Journal of Nanotechnology, vol. 2, pp. 72-77, 2021, doi: 10.1109/OJNANO.2021.3109897.
[29] M. S. Kavrik et al., "Ultralow Defect Density at Sub-0.5 nm HfO2/SiGe Interfaces via Selective Oxygen Scavenging," ACS Applied Materials & Interfaces, vol. 10, no. 36, pp. 30794-30802, 2018/09/12 2018, doi: 10.1021/acsami.8b06547.
[30] Y.-W. Lin et al., "Self-induced ferroelectric 2-nm-thick Ge-doped HfO2 thin film applied to Ge nanowire ferroelectric gate-all-around field-effect transistor," Applied Physics Letters, vol. 117, no. 26, 2020, doi: 10.1063/5.0029628.
[31] S. Ogawa et al., "Insights into thermal diffusion of germanium and oxygen atoms in HfO2/GeO2/Ge gate stacks and their suppressed reaction with atomically thin AlOx interlayers," Journal of Applied Physics, vol. 118, no. 23, 2015, doi: 10.1063/1.4937573.
 
 
 
 
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