近年來，不論是雲端網路以及物聯網等的發展都逐漸普及且成熟，因此在科技與半導體產業的發展也越來越快。而在半導體產業中隨著摩爾定律的發展，在一個集成電路上我們期望可以放置更高密集且低功耗的元件，然而傳統的FinFET半導體結構已經逐漸遇到物理上的極限以及製程技術的困難。為了改善元件結構微縮上的問題，許多研究團隊紛紛提出許多可以持續摩爾定律發展的研究，例如:使用更高載子遷移率的通道材料(如：矽鍺、鍺、三五族化合物等)來取代傳統的通道材料矽，或是透過二維及三維的電晶體結構來改善並提高元件的性能。
在本研究中，我們提出自我對準的製程技術來做出上層為鍺(110)表面取向的方形鍺奈米線作為PFET，以及下層為鍺(111)表面取向的菱形鍺奈米線結構作為NFET的互補式場效電晶體(Complementary Field-Effect Transistor, CFET)，透過此CFET的結構，可以有效地將元件尺寸微縮一半，此外我們透過單一金屬閘極來有效的簡化此結構的製程，且在CFET結構的PFET與NFET中，當|VD| = 0.05V時，其ION/IOFF值分別為1.72⨯105與1.57⨯106，其SS最小值(SSmin)分別為104 mV/dec與110 mV/dec，而在|VD| = |VG-VTH| = 0.5V時，其ION值分別為86 μA/μm 與13 μA/μm。此外，我們也做了Inverter特性上的分析，當VDD = 0.7 V時，其電壓增益值為18 V/V。
最後，我們透過半導體模擬軟體TCAD進行此CFET結構的模擬，當金屬功函數為4.33 eV 時，其NFET與PFET具有最對稱的|VTH| = 0.25 V與ION值，且在Inverter的模擬中，其展現良好的電壓傳輸特性曲線，在VDD為0.5 V時，擁有最高的電壓增益值為297 V/V，且在SRAM的模擬中在VDD為0.5V時，其SNM為90 mV。根據這些模擬的結果，當我們在此結構中得到對稱的電性，可以有效地提升元件性能，並持續的退進摩爾定律。

In recent years, the development of technologies such as cloud computing and the Internet of Things (IoT) has become increasingly widespread and mature. Consequently, the advancements in technology and the semiconductor industry have accelerated. In the semiconductor industry, as Moore's Law continues to progress, there is a desire to place higher-density and low-power components on integrated circuits. However, traditional FinFET semiconductor structures have reached physical limitations and encountered challenges in manufacturing processes. To address the scaling issues of structures, many research teams have proposed various studies to sustain the development of Moore's Law. For example, using channel materials with higher carrier mobility, such as (SiGe, Ge, III-V compound semiconductors) to replace the conventional silicon channel material, or improving and enhancing component performance through two-dimensional and three-dimensional transistor structures.
In this study, we propose a self-aligned manufacturing technique to create a CFET structure, with a square Ge nanowire aligned to the (110) surface orientation serving as the PFET and a diamond-shaped Ge nanowire aligned to the (111) surface orientation serving as the NFET. Using CFET structures can effectively shrink the device area by half.. Additionally, we simplify the manufacturing process of this structure by employing a single metal gate. In the CFET structure, the PFET and NFET exhibit respective values of ION/IOFF as 1.72×105 and 1.57×106 when |VD| = 0.05 V. The minimum subthreshold swing (SSmin) values are 104 mV/dec and 110 mV/dec, respectively. When |VD| = |VG-VTH| = 0.5V, the ION values are 86 μA/μm and 13 μA/μm for PFET and NFET, respectively. Furthermore, an analysis of inverter characteristics demonstrates a voltage gain of 18 V/V when VDD = 0.7V.
Finally, we simulated CFET structures by TCAD software. When the metal work function is 4.33 eV, the NFET and PFET exhibit the most symmetrical |VTH| = 0.25V and ION values. In the inverter simulation, it shows excellent voltage transfer characteristics, with the highest voltage gain of 297 V/V at VDD = 0.5V. In the SRAM simulation, the static noise margin (SNM) is 90 mV at VDD = 0.5V. Based on these simulation results, when we achieve symmetrical electrical characteristics in this structure, it can effectively enhance the performance of components and sustain the progression of Moore's Law.

中文摘要 i
Abstract iii
誌謝 v
目錄 vi
表目錄 vii
圖表目錄 viii
第一章 1
簡介 1
1-1摩爾定律的微縮 (Moore's law) 1
1-2高電子、電洞遷移率之通道材料 4
1-3 High-K材料的應用 5
1-4垂直式堆疊互補式場效電晶體 7
1-5矽、鍺不同表面取向之載子遷移率比較 10
1-6通道與閘極氧化層的界面處理 12
1-7霍爾效應量測 14
1-8研究動機 15
1-9論文組織 18
第二章 20
MOSFET與CMOS之操作機制及重要參數 20
2-1金氧半場效電晶體(MOSFET) 20
2-2 CMOS Inverter 23
2-3 MOSFET之重要參數 25
2-3.1 次臨界斜率(Subthreshold swing, SS) 25
2-3.2 臨界電壓(Threshold voltage, VTH) 26
2-3.3 電壓增益(Voltage gain) 28
第三章 29
自我對準鍺奈米線之互補式場效電晶體 29
3-1自我對準鍺奈米線之互補式場效電晶體製程流程 29
3-2 CFET結構之材料分析 35
3-2-1霍爾量測(Hall-effet)分析 35
3-2-2 CFET結構之SEM、TEM及EDS分析 38
3-3 CFET結構中PFET與NFET及其Inverter電性分析 42
3-3-1 CFET結構中的PFET與NFET 42
3-3-2 CFET結構中的Inverter特性 48
第四章 50
TCAD模擬自我對準鍺奈米線之互補式場效電晶體 50
4-1 CFET結構的架設及物性分析 50
4-1.1 CFET結構的架設 50
4-1.2 CFET 結構的物性 52
4-2 TCAD模擬之CFET電性分析 55
4-2.1 CFET 的IDVG及IDVD特性曲線 55
4-2.2 CFET 的Inverter VTC曲線及電壓增益 57
4-2.3 CFET 的SRAM曲線 59
第五章 62
結論 62
參考文獻 65

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第二章
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第五章
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