2.5D 系統級封裝 (SiP) 設計架構具有良好的 IP 複用性以及高頻寬密度的異質整合性等方面的特點，因而廣受歡迎；且 SiP 有相對較低設計成本及較短的設計週期，備受業界推崇與青睞。

然而，晶片封裝間隙和引腳間距已來到亞微米等級，封裝的設計對系統效能的影響已不可忽略，且由於系統效能和設計靈活性之間的權衡與取捨，使得異質整合技術開發面臨相當大的困難。在市場需求居高不下的情況，各界必須建立更高端的方法來偕同最佳化小晶片 (chiplet) 系統設計，而非遵循缺乏封裝和小晶片整體視圖的傳統 Die-by-die 設計架構。

在本論文中，我們提出了一種備有重分佈層 (Redistribution Layer, RDL) 繞線器的小晶片封裝偕同設計流程。從封裝和小晶片中一起做時序環境萃取開始，然後是引腳選擇策略和封裝繞線器。這種基於網絡流的繞線器是由網格模型構建的，該模型提供了一種可在一個步驟中，在具有任意數量的小晶片和 RDL 的框架中找到最小化總線長及可控的鑽孔 (Via) 數量的解，從而提高性能改進，而不採用較為啟發式的兩步驟的逃逸繞線及全局繞線演算法。

在實驗中，我們以 2D 架構相對應設計的系統效能 400 MHz 與 Die-by-die 設計法的系統效能 349 MHz 的差作為 100% 的基準，即我們的最大可能改善空間。最終舊的設計流程的系統性能差僅能達到 26% ；而新的設計流程可將系統性能差可以進一步縮小到僅僅 2% ，幾乎等同於 2D 設計的系統效能。

2.5 D System-in-Package (SiP) design has gained much popularity for its features in IP reuse, heterogeneous integration with high bandwidth density, etc. The industry has benefited from lower design costs and shorter design cycles with SiP. While the chip-package gap and pin pitch are shrinking down to sub-micron scale, package design became tremendously significant to the system performance.

However, heterogeneous integration faces difficulties due to challenges in balancing performance and design flexibility. It is urged to establish more sophisticated approaches to co-optimize the package and chiplet designs rather than following the conventional die-by-die approach which lacks the holistic view of package and chiplets.

In this thesis, a chiplet-package co-design flow with an embedded network-flow based redistribution layer (RDL) router is proposed. It starts from the timing context extraction together from the package and chiplets and is followed by a pin selection strategy and a package router. This network-flow based router is constructed by a grid model which provides an approach for finding a routing solution in global routing stage with an objective of minimizing total wirelength and controllable via usage and thus could favor performance improvement, instead of doing a two-step escape-and-global routing.

Through experiments, the new design flow shows that the system performance gap can be closed to 2% while an old design flow can achieve only 26%, by taking the performance difference of a 2D counterpart to a die-by-die design as the baseline.

Abstract (Mandarin) I
Abstract II
Acknowledgements III
Contents IV
List of Figures VI
List of Tables VIII

1 Introduction 1

2 Preliminaries and Problem Formulation 5
2.1 Problem Formulation . . . 5
2.2 Routing Algorithm Overview . . . 6
2.3 Minimum-Cost Maximum-Flow Algorithm . . . 7
2.4 Wire Timing Budget . . . 8

3 Methodology 9
3.1 Pin Assignment . . . 10
3.2 Grid Model . . . 11
3.3 Multi-pin Net . . . 13
3.4 Signal Assignment . . . 13
3.5 Compaction Method . . . 15

4 Experimental Case Study 18
4.1 Experimental Case Study . . . 18
4.2 System Architecture and Technology Settings . . . 18
4.3 Design Cases . . . 19
4.3.1 Case-1: Reference 2D Design . . . 19
4.3.2 Case-2: Context-Free 2.5D Design . . . 21
4.3.3 Case-3: Context-Aware Optimized 2.5D Designs . . . 21

5 Experimental Results 23
5.1 Maximum Frequency . . . 24
5.2 System Power and Wirelength . . . 26
6 Conclusions 28
Bibliography 29

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