隨者人工智慧近幾年來的興起與技術的發展，創造了許多新型的應用，其中仿神經系統，可以透過將參數以類比值的形式儲存於電晶體懸浮閘內，不用經過類比數位轉換便可直接儲存並執行運算，同時非揮發性記憶體的特色，可以使運算出的類比參數值長久的儲存，而不需要重新訓練。
本研究的目標為使用標準邏輯製程做出能儲存類比值的非揮發性記憶體，透過事先使用軟體模擬演算法，得知十位元的解析度才能使仿神經系統訓練收斂，故本研究設計原則注重在非揮發性及具備高解析度兩項特性上，我們先設計並模擬出一個具備讀、寫、相容於仿神經系統演算法功能等三個功能模式的單一顆類比記憶體單元，確定了單一顆類比記憶體單元的可行性後，為了儲存更多資訊量以增加記憶體的實用性，我們再進一步將單一顆類比記憶體單元與解碼器、多工器等周邊電路做結合，最終設計出在台積電標準0.18微米製程下，並具有十位元以上解析度的完整非揮發性類比記憶體陣列。最後透過下線量測晶片並與電路模擬結果做比較，驗證下線回來的晶片是否符合模擬時的設計。
最後，在研究過程中，我們激盪出了更多可以突破的問題與想法，在論文最後的部分將提出來並作探討。

With the rise and development of artificial intelligence (AI) in recent years, many new applications have been created. Among them, the neuromorphic system can store parameters in analog form inside the floating gate of a transistor, which can be directly stored and executed without analog-to-digital conversion. At the same time, the non-volatile memory feature can make the computed analog parameter values be stored for a long time without retraining.
The goal of this study is to create a non-volatile memory that can store analog values using standard CMOS logic processes. Through software simulation of the algorithm, it was found that a ten-bit resolution is needed to make the neuromorphic system training converge. Therefore, the design principle of this thesis focuses on the two characteristics of non-volatile and high resolution. Firstly, a single analog memory cell with three functional modes, including read, write, and compatible with the neuromorphic system algorithm, was designed and simulated. After confirming the feasibility of a single analog memory cell, in order to store more information and increase the practicality of the memory, we further integrated the single analog memory cell with peripheral circuits such as decoders and multiplexers. Finally, a complete non-volatile analog memory array with a resolution of ten bits or more was designed in the TSMC standard 0.18-micron process. Finally, by measuring the chip and comparing it with the circuit simulation results, the chip can be verified to check whether it meet the design of the simulation.
In the research process, we have also proposed and discussed more problems and ideas for breakthroughs in the final part of the paper.

摘要 ------------------------------------------------------------I
Abstract -------------------------------------------------------II
致謝 ----------------------------------------------------------III
章節目錄 --------------------------------------------------------IV
圖目錄 ---------------------------------------------------------VI
表格目錄 ------------------------------------------------------VIII
第一章 前言 ----------------------------------------------------1
1.1 研究動機與目的 -----------------------------------------------1
1.2 研究貢獻 ----------------------------------------------------2
1.3 章節架構 ----------------------------------------------------3
第二章 相關文獻回顧 ---------------------------------------------4
2.1 非揮發性懸浮閘記憶體寫入和抹除原理 ----------------------------4
2.1.1 熱載子效應 (Hot Carrier Effect) ---------------------------5
2.1.2 傅勒-諾德翰穿隧效應 (Fowler-Nordheim Tunneling Effect) -----9
2.2 懸浮閘元件量測和懸浮閘模型建立 ---------------------------------9
2.2.1 HSPICE 閘極電流模擬熱載子電流模型 ---------------------------9
2.2.2 HSPICE 閘極電流模擬傅勒-諾德翰穿隧電流模型 -----------------12
2.3 不同類比非揮發性記憶體寫入之架構 ------------------------------13
2.3.1 標準製程下多準位類比記憶體 ---------------------------------13
2.3.2 自我收斂平衡電流型儲存記憶體 --------------------------------15
2.3.3 比較器負回授線性寫入類比記憶體 ------------------------------17
2.4 脈衝時序依賴可塑性學習演算法 ----------------------------------19
2.5 總結 --------------------------------------------------------20
第三章 類比記憶體單元電路設計 ------------------------------------21
3.1 類比記憶體單元核心設計概念及架構 ------------------------------21
3.2 類比記憶體子電路 --------------------------------------------27
3.2.1 電壓電平轉換器(Level shifter) -----------------------------27
3.2.2 操作放大器(Operational amplifier) --------------------------29
3.2.3 電流源電路(Current reference circuit) ----------------------30
3.3 類比記憶體單元模擬結果 ----------------------------------------31
3.4 類比記憶體單元模擬結果討論 -------------------------------------35
3.5 總結 ---------------------------------------------------------36
第四章 類比記憶體陣列電路設計 -------------------------------------37
4.1 類比記憶體陣列架構 --------------------------------------------37
4.2 類比記憶體陣列模擬結果 ----------------------------------------39
4.3 類比記憶體陣列佈局介紹 ----------------------------------------41
4.4 總結 ---------------------------------------------------------44
第五章 量測結果 -------------------------------------------------45
5.1 電壓電平轉換器量測結果 ----------------------------------------45
5.2 雙向線性寫入演算法模式量測結果 ---------------------------------47
5.3 寫入特定類比值模式量測結果 -------------------------------------50
5.4 類比記憶體懸浮閘漏電問題 ---------------------------------------51
5.5 不同架構間效能比較討論 -----------------------------------------52
5.6 懸浮閘漏電問題之改善方式 ---------------------------------------53
5.7 總結 ---------------------------------------------------------55
第六章 結論與未來展望 --------------------------------------------56
6.1 結論 ---------------------------------------------------------56
6.2 未來展望 -----------------------------------------------------56
參考文獻 ----------------------------------------------------------57

[1] S. Tam, P.-K. Ko and C. Hu, "Lucky-electron model of channel hot-electron injection in MOSFET'S", IEEE Transactions on Electron Devices, vol. 31, no. 9, pp. 1116-1125, Sep 1984.
[2] K.-H. Lee, S.-C. Wang and Y.-C. King, "Self-convergent scheme for logic-process-based multilevel/analog memory", IEEE Trans. Electron Devices, vol. 52, no. 12, pp. 2676-2681, Dec. 2005.
[3] Charles Ching-Hsiang Hsu, “Logic Non-volatile Memory: The NVM Solutions from eMemory”, 2014.
[4] Chen-Hsin Lien, Logic Non-Volatile Memory course lecture notes, 2022.
[5] 陳珮琳, 嵌入式電流模式非揮發性類比記憶體研發, 碩士論文, 國立清華大學, 2010
[6] C. Diorio, D. Hsu and M. Figueroa, "Adaptive CMOS: From biological inspiration to systems-on-a-chip", Proc. IEEE, vol. 90, no. 3, pp. 345-357, Mar. 2002.
[7] C. Huang, P. Sarkar and S. Chakrabartty, "Rail-to-rail linear hot-electron injection programming of floating-gate voltage bias generators at 13-bit resolution", IEEE Journal of Solid-State Circuits, vol. 46, no. 11, pp. 2685-2692, 2011.
[8] D. H. Kang, H. G. Jun, K. C. Ryoo, H. Jeong and H. Sohn, "Emulation of spike-timing dependent plasticity in nano-scale phase change memory", Neurocomputing, vol. 155, pp. 153-158, 2015.
[9] 周柏睿, 類比記憶體實現具備權重更新行為突觸電路, 碩士論文, 國立清華大學, 2022.
[10] S. Chakrabartty and G. Cauwenberghs, “Fixed-current method for programming large floating-gate arrays,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), Jul. 2005, pp. 34–39.
[11] A. Bandyopadhyay, G. J. Serrano, and P. Hasler, “Adaptive algorithm using hot-electron injection for programming analog computational memory elements within 0.2% of accuracy over 3.5 decades,” IEEE J. Solid-State Circuits, vol. 41, no. 9, pp. 2107–2114, Sep. 2006.
[12] A. Basu and P. E. Hasler, “A fully integrated architecture for fast and accurate programming of floating gates over six decades of current,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 6, pp. 953–962, Jun. 2011.
[13] S. Kinoshita, T. Morie, M. Nagata, and A. Iwata, “A PWM analog memory programming circuit for floating-gate MOSFETs with 75- s programming time and 11-bit updating resolution,” IEEE J. Solid-State Circuits, vol. 36, no. 8, pp. 1286–1290, Aug. 2001.
[14] Y. L.Wong, M. H. Cohen, and P. A. Abshire, “A floating-gate comparator with automatic offset adaptation for 10-bit data conversion,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 7, pp. 1316–1326, Jul. 2005.