本論文使用了四種不同磊晶結構的氮化鎵(GaN)矽基板試片，並以氧化銦錫(ITO)作為p型氮化鎵(p-GaN)元件之歐姆接觸閘極金屬及氮化鈦(TiN)作為p型氮化鎵 gate元件之蕭特基接觸閘極金屬，製作出p型氮化鎵高電子遷移率電晶體(p-GaN gate HEMTs)。四種磊晶結構之主要差別為p-GaN中的鎂摻雜濃度、於p-GaN與AlGaN之間添加一層氮化鋁(AlN)。
三種不同p-GaN之鎂摻雜濃度試片所製作出的ITO閘極元件之臨界電壓由小至大分別為1.4 V、1.5 V、1.9 V，而四種試片所製作出的TiN閘極元件之臨界電壓由小至大分別為1.5 V、1.6 V、1.9 V、-0.1 V，實驗中發現藉由p-GaN中的鎂摻雜濃度提升，可以有效的提升臨界電壓，但AlN的加入會造成臨界電壓位移。另外，本實驗進一步對元件進行可靠度研究，發現以TiN作為蕭特基閘極接觸金屬在閘極電壓崩潰電壓及閘極電壓階梯式應力等可靠度測試中比ITO作為歐姆接觸閘極金屬擁有更好之元件特性，但是隨著p-GaN中的鎂摻雜濃度提升，TiN閘極元件會提早失效，而ITO閘極元件展現了良好的電壓穩定性。

In this study, we demonstrated ITO ohmic electrode and TiN schottky electrode for p-GaN gate high electron mobility transistors with four different GaN-on-Si epitaxial structures. The structural differences between these four epi-wafers are the magnesium doping concentration of the p-GaN layer and the insertion of an AlN layer between p-GaN and AlGaN.
The ITO gate with three different magnesium doping concentrations of p-GaN layer shows threshold voltages of 1.4 V, 1.5 V, and 1.9 V, respectively, and the TiN gate with four fabricated devices shows threshold voltages of 1.5 V, 1.6 V, 1.9 V, and -0.1 V, respectively. The threshold voltage can be increased by increasing the magnesium doping concentration of p-GaN layer, but the insertion of an AlN layer will cause threshold voltage shift. Furthermore, preliminary reliability of the fabricated devices were investigated, and it was found that TiN schottky contact show better reliability than ITO ohmic contact from gate breakdown measurement and gate step-stress measurement. However, increasing the doping concentration of the p-GaN layer would cause TiN gate breakdown at a lower voltage, while the ITO gate shows better robustness.

中文摘要 i
Abstract ii
目錄 iii
圖目錄 vi
表目錄 xii
1 第一章 序論 1
1.1 前言 1
1.2 氮化鎵材料特性介紹 2
1.2.1 自發性極化效應 2
1.2.2 壓電性極化效應 4
1.2.3 氮化鋁鎵/氮化鎵異質結構 5
1.3 文獻回顧 6
1.3.1 氮化鋁鎵/氮化鎵高電子遷移率電晶體 6
1.3.2 P型氮化鎵閘極高電子遷移率電晶體 7
1.3.3 P型氮化鎵閘極接觸 9
1.4 研究方向簡介 10
1.4.1 研究動機 10
1.4.2 論文架構 11
2 第二章 原理簡介 12
2.1 P型氮化鎵覆蓋層 12
2.2 P型氮化鎵自我對準蝕刻製程 13
2.3 P型氮化鎵閘極接觸 18
2.4 實驗設計 18
3 第三章元件製作流程 19
3.1 晶圓之磊晶結構 19
3.2 P-GaN gate HEMT元件製作流程 20
3.2.1 試片清潔(Sample cleaning) 21
3.2.2 蝕刻對準記號(Alignment mark formation) 22
3.2.3 元件隔離(Device isolation) 23
3.2.4 閘極金屬沉積(Gate metal deposition) 25
3.2.5 閘極金屬蝕刻(Gate metal etching) 26
3.2.6 p-GaN蝕刻(P-GaN etching) 29
3.2.7 源極/汲極歐姆接觸金屬(Source/drain ohmic contact) 30
3.2.8 襯墊金屬(Pad metal) 32
3.2.9 鈍化層(Surface passivation)及第二層襯墊金屬 32
3.3 元件尺寸與影像 34
3.3.1 元件規格 34
4 第四章 元件量測與結果分析 35
4.1 TLM(Transfer length method)測試結構量測 35
4.1.1 2DEG TLM量測 35
4.2 ITO gate HEMT 量測結果 40
4.2.1 ITO/p-GaN TLM量測 40
4.2.2 閘極與源極間P-N接面量測 43
4.2.3 相同Lgd之汲極電流對閘極電壓特性曲線(Id-Vg) 44
4.2.4 相同Lgd之汲極電流對汲極電壓特性曲線(Id-Vd) 47
4.3 TiN gate HEMT 量測結果 50
4.3.1 相同Lgd之汲極電流對閘極電壓特性曲線(Id-Vg) 50
4.3.2 相同Lgd之汲極電流對汲極電壓特性曲線(Id-Vd) 53
4.4 HEMT閘極可靠度量測 57
4.4.1 閘極崩潰電壓(Gate breakdown)量測 57
4.4.2 閘極電壓階梯式應力(Gate step-stress)可靠度量測 68
5 第五章 結論與未來展望 87
參考文獻 88

[1] B. J. Baliga, “Power semiconductor device figure of merit for high-frequency applications,” IEEE Electron Device Letters, vol. 10, no.10, pp. 455 - 457, Oct. 1989.
[2] R. F. Davis, J. W. Palmoue and J. A. Edmond, “A review of the status of diamond and silicon carbide devices for high-power, -temperature, and –frequency applications,” International Technical Digest on Electron Devices, Dec. 1990.
[3] O. Ambacher, J. Smart, J. R. Shealy, N. G. Weimann, K. Chu, M. Murphy, W. J. Schaff, and L. F. Eastman, R. Dimitrov, L. Wittmer, and M. Stutzmann, W.Rieger and J. Hilsenbeck, “Two-dimensional electron gases induced by spontaneous and piezoelectric polarization charges in N- and Ga-face AlGaN/GaN heterostructures,” Journal of Applied Physics, vol. 85, no.6, pp. 3222 - 3233, Mar. 1999.
[4] F. Sacconi, A. D. Carlo, P. Lugli, and H. Morkoç, “Spontaneous and Piezoelectric Polarization Effects on the Output Characteristics of AlGaN/GaN Heterojunction Modulation Doped FETs,” IEEE Transactions on Electron Devices, vol. 48, no.10, pp. 450 - 457, Mar. 2001.
[5] M. A. Khan, J. N. Kuznia, J. M. V. Hove, N. Pan, and J. Carter, “Observation of a Two‐Dimensional Electron Gas in Low Pressure Metalorganic Chemical Vapor Deposited GaN‐AlxGa1−xN Heterojunctions,” Applied Physics Letters, vol. 60, no. 24, pp. 3027 - 3029, Mar. 1992.
[6] M. A. Khan, A. Bhattarai, J. N. Kuznia, and D. T. Olson, “High electron mobility transistor based on a GaN‐AlxGa1−xN heterojunction,” Applied Physics Letters, vol. 63, no. 9, pp. 1214 - 1215, Jun. 1993.
[7] S. Joblota, F. Semond, Y. Cordier, P. Lorenzini, and J. Massies, “High-electron-mobility AlGaN/GaN heterostructures grown on Si (001) by molecular-beam epitaxy,” Applied Physics Letters, vol. 87, no.13, pp. 133505, Sep. 2005.
[8] X. Hu, G. Simin, J. Yang, M. A. Khan, R. Gaska, and M. Shur, “Enhancement mode AlGaN/GaN HFET with selectively grown pn junction gate,” Electronics Letters, vol. 36, no. 8, p. 753 - 754, Apr. 2000.
[9] D. Buttari, A. Chini, A. Chakraborty, L. McCarthy, H. Xing, T. Palacios, L. Shen, S. Keller, U.K. Mishr, “Selective dry etching of GaN over AlGaN in BCl3/SF6 mixtures,” International Journal of High Speed Electronics and Systems, vol. 14, no. 3, p. 756 - 761, Aug. 2004.
[10] Hsien-Chin Chiu, Yi-Sheng Chang, Bo-Hong Li, Hsiang-Chun Wang, Hsuan-Ling Kao, Feng-Tso Chien, Chih-Wei Hu, Rong Xuan, “High Uniformity Normally-OFF p-GaN Gate HEMT Using Self-Terminated Digital Etching Technique,” IEEE Transactions on Electron Devices, vol. 65, no. 11, p. 4820 - 4825, Nov.2018.
[11] A. N. Tallarico, S. Stoffels, P. Magnone, N. Posthuma, E. Sangiorgi, S. Decoutere, and C. Fiegna, "Investigation of the p-GaN Gate Breakdown in Forward-Biased GaN-Based Power HEMTs," IEEE Electron Device Letters, vol. 38, no. 1, pp. 99 - 102, Nov. 2017.
[12] L. Sayadi, G. Iannaccone, S. Sicre, O. Häberlen, and G. Curatola, “Threshold voltage instability in p-GaN gate AlGaN/GaN HFETs, ” IEEE Transactions on Electron Devices, vol. 65, no. 6, pp. 2454 - 2460, Jun. 2018.
[13] T.-L. Wu, D. Marcon, S. You, N. Posthuma, B. Bakeroot, S. Stoffels, M. V. Hove, G. Groeseneken, and S. Decoutere, “Forward bias gate breakdown mechanism in enhancement-mode p-GaN gate AlGaN/GaN high electron mobility transistors,” IEEE Electron Device Letters, vol. 36, no. 10, pp. 1001 - 1003, Oct. 2015.
[14] M. Ruzzarin, M. Meneghini, A. Barbato, V. Padovan, O. Haeberlen, M. Silvestri, T. Detzel, G. Meneghesso, and E. Zanoni, “Degradation mechanisms of GaN HEMTs with p-type gate under forward gate bias overstress,” IEEE Transactions on Electron Devices, vol. 65, no. 7, pp. 2778 - 2783, Jul. 2018.
[15] Chih-Yao Chang, Yao-Luen Shen, Ching-Yao Wang, Shun-Wei Tang, Tian-Li Wu, Wei-Hung Kuo, Suh-Fang Lin, Chih-Fang Huang, “Investigation on Stability of p-GaN HEMTs With an Indium–Tin–Oxide Gate Under Forward Gate Bias,” IEEE Journal of the Electron Devices Society, vol. 9, pp. 687 – 690, Jul. 2021.
[16] G. Greco, F. Iucolano, and F. Roccaforte, “Review of technology for normally-off HEMTs with p-GaN gate,” Materials Science in Semiconductor Processing, vol. 78, pp. 96 - 106, May. 2018.
[17] K.-M. Chang, J.-Y. Chu, and C.-C. Cheng, “Investigation of indium– tin-oxide ohmic contact to p-GaN and its application to high-brightness GaN-based light-emitting diodes,” Solid-State Electronics, vol. 49, no. 8, pp. 1381 - 1386, Aug. 2005
[18] A. Nigam, T. N. Bhat, S. Rajamani, S. B. Dolmanan, S. Tripathy, and M. Kumar, “Effect of self-heating on electrical characteristics of AlGaN/ GaN HEMT on Si (111) substrate,” AIP Advances, vol. 7, no. 8, p. 085015, Aug. 2017.
[19] M. Tapajna, O. Hilt, E. Bahat-Treidel, J. Wurfl, and J. Kuzmik, “Gate Reliability Investigation in Normally-Off p-Type-GaN Cap/AlGaN/GaN HEMTs Under Forward Bias Stress,” IEEE Electron Device Letters, vol. 37, no. 4, pp. 385–388, April. 2016.