影像感測器在現代電子裝置中扮演著重要的角色，隨著科技的發展，這些電子裝置對於影像解析度的需求也日益增加。傳統應用於影像感測器後端之類比數位轉換器，主要採用單斜率轉換器架構，其電路優勢在於架構簡單，且轉換器之間的偏差校準方便。然而，單斜率轉換器卻易受電路雜訊限制，而難以在解析度的表現上進一步突破，為了滿足更高解析度之影像感測器需求，本篇碩士論文提出一個具有零靜態功率消耗之過取樣連續漸進式類比數位轉換器，可應用於高解析度CMOS影像感測器後端作為訊號轉換電路。為了精確的轉換訊號，並同時維持低功率消耗特性，本次設計之類比數位轉換器電路使用了資料加權平均技術以及誤差調變技術，並將其與被動式雜訊調變架構相結合，使得類比數位轉換器可免去主動式雜訊調變架構中所需求的放大器電路，進而達到零靜態功率消耗的目標。本次設計同時也使用到二階段式轉換器架構，並在快閃式類比數位轉換器之分壓電阻前加入了電流控制開關，使其在電路非運作時不消耗靜態功率。在模擬結果方面，本篇碩士論文提出之過取樣類比數位轉換器以90奈米製程設計，操作於10MS/s取樣頻率，核心電路消耗281. 3μW，並在頻寬為312.5kHz情況下達到12位元有效位數。在量測結果中，整體晶片包括部分驅動電路，共消耗477.03μW。在頻寬為312.5kHz情況下有效位數為10.17位元，持續縮減頻寬至156.25kHz，有效位數可達11.67位元。

CMOS image sensor has played an important role in electronic devices such as computers, smartphones or notebooks. As the development of social media, picture and video require higher resolution to the data converter in CMOS image sensor. In conventional design, single-slope analog-to-digital converters (ADC) are commonly used in the backend of CMOS image sensor for data conversion. However, it is difficult for a single-slope ADC to provide more than 10 bits effective number of bits (ENOB) due to circuit noise issue. On the other hand, successive approximation register (SAR) ADC can achieve more than 10 bits ENOB by introducing several kinds of oversampling technique.
In this thesis, a zero static power oversampling SAR ADC is proposed for CMOS image sensor application. For more precise conversion of signal with low power consumption, the proposed SAR ADC employs Passive Noise Shaping structure combined with Data Weighted Averaging (DWA) and Mismatch Error Shaping (MES) techniques. With the passive noise shaping structure, the oversampling SAR ADC does not need operational amplifier (OPAMP) for integrator, thus consuming low power. Meanwhile, a zero static current flash ADC is proposed to be the coarse ADC in the two-stage flash-SAR structure. In simulation results, the oversampling SAR ADC operates at 10 MS/s, consumes 281.3 μW and achieves 12-ENOB in 312.5kHz bandwidth in post-simulation under the TSMC 90-nm fabrication. In measurement results, the whole chip consumes 477.03 μW, including a part from buffer circuits, and achieves 10.17-ENOB in 312.5kHz bandwidth and 11.67-ENOB in 156.25kHz bandwidth.

摘要 i
Abstract ii
致謝 iii
圖目錄 vi
表目錄 viii
第一章 緒論 1
1.1 研究背景 1
1.2 研究動機 2
1.3 論文章節架構 3
第二章 連續漸進式類比數位轉換器 4
2.1 連續漸進式切換機制 4
2.1.1 傳統切換與單調(Monotonic)切換 4
2.1.2 C-DAC電荷注入 5
2.2 轉換器規格介紹 6
2.3 過取樣與雜訊調變 7
2.4 二階段式轉換器架構 8
第三章 電路架構 9
3.1 過取樣類比數位轉換器架構 9
3.2 靴帶式開關取樣電路 10
3.3 快閃式類比數位轉換器 10
3.4 資料加權平均 11
3.5 誤差調變 13
3.6 被動雜訊調變 15
3.7 電容陣列 16
3.8 動態比較器電路 17
3.9 連續漸進式轉換邏輯 18
3.10 數位錯誤校正電路 19
第四章 模擬與佈局 21
4.1 設計流程 21
4.2 模擬方法與環境介紹 22
4.3 Pre simulation 24
4.3.1 線性度與功耗表現 24
4.3.2 電容不匹配影響 28
4.3.3 DWA與MES效果 30
4.3.4 Flash ADC誤差控制 31
4.4 佈局介紹 32
4.4.1 比較器 32
4.4.2 Flash ADC 33
4.4.3 電容陣列 34
4.4.4 長距離走線 34
4.4.5 整體電路佈局 35
4.5 Post simulation 36
4.6 模擬結果與文獻比較 37
第五章 量測環境設計與結果 39
5.1 印刷電路板(Printed Circuit Board, PCB)設計 39
5.1.1 PCB Schematic 39
5.1.2 PCB Layout 40
5.2 量測設定 41
5.3 量測結果與討論 43
5.3.1 模擬與量測結果比較 43
5.3.2 雜訊來源驗證 44
5.3.3 製程變異與電路表現關係 46
5.3.4 不同輸入頻率比較 49
5.3.5 功率消耗 50
第六章 總結與研究建議 51
6.1 總結 51
6.2 後續研究建議 52
6.2.1 電路輸出解析度 52
6.2.2 C-DAC電容種類選擇 53
6.2.3 靜態功率消耗 54
6.2.4 數位類比之間的雜訊隔絕 55
參考文獻 57
附錄 量測資料 59

[1] Wu, J.-T., Analog-Digital Interfaces. Data-Conversion Integrated Circuits, April 29, 2020.
[2] Chin-Yu Lin, Y.-Z.L., Chih-Hou Tsai, Chao-Hsin Lu, An 80MHz-BW 640MS/s Time-Interleaved Passive Noise-Shaping SAR ADC in 22nm FDSOI Process in IEEE International Solid- State Circuit Conference - (ISSCC). 2021. pp. 378-380.
[3] Lu Jie, B.Z., Michael P. Flynn, A 50MHz-Bandwidth 70.4dB-SNDR Calibration-Free Time-Interleaved 4th-Order Noise-Shaping SAR ADC, in IEEE International Solid- State Circuit Conference - (ISSCC). 2019. pp. 332-334.
[4] Shu, Y.-S., L.-T. Kuo, and Tien-Yu Lo, An Oversampling SAR ADC With DAC Mismatch Error Shaping Achieving 105 dB SFDR and 101 dB SNDR Over 1 kHz BW in 55 nm CMOS. IEEE Journal of Solid-State Circuits, 2016. 51(12): pp. 2928-2940.
[5] Ying-Zu Lin, C.-Y.L., Shan-Chih Tsou, Chih-Hou Tsai, Chao-Hsin Lu, A 40MHz-BW 320MS/s Passive Noise-Shaping SAR ADC with Passive Signal-Residue Summation in 14nm FinFET, in IEEE International Solid- State Circuit Conference - (ISSCC). 2019. pp. 330-332.
[6] Liu, C.-C., et al., A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure. IEEE Journal of Solid-State Circuits, 2010. 45(4): pp. 731-740.
[7] Chin-Yu Lin , Y.-H.W., and Tai-Cheng Lee, A 10-bit 2.6-GS/s Time-Interleaved SAR ADC With a Digital-Mixing Timing-Skew Calibration Technique. IEEE Journal of Solid-State Circuits, 2018. 53(5): pp. 1508-1517.
[8] HAE-SEUNG LEE, D.A. HODGES, and PAUL R. GRAY, A Self-Calibrating 15 Bit CMOS A/D Converter. IEEE Journal of Solid-State Circuits, 1984. 19(6): pp. 813-819.
[9] Fredenburg, J.A. and M.P. Flynn, A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC. IEEE Journal of Solid-State Circuits, 2012. 47(12): pp. 2898-2904.
[10] Ying-Zu Lin, C.-C.L., A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS. IEEE trANSACTIONS ON CIRCUITS AND SYSTEMS I: Regular Papers, 2013. 60(3): pp. 570-581.
[11] Chun-Cheng Liu, C.-H.K., Ying-Zu Lin, A 10 bit 320 MS/s Low-Cost SAR ADC for IEEE802.11ac Applications in 20 nm CMOS. IEEE Journal of Solid-State Circuits, 2015. 50(11): pp. 2645-2654.
[12] Razavi, B., The Bootstrapped Switch [A Circuit for All Seasons], in IEEE Solid-State Circuits Magazine. Summer 2015. pp. 12-15.
[13] Yan Huang, H.S., Dirk Killat, Design and Analysis of Novel Dynamic Latched Comparator with Reduced Kickback Noise for High-speed ADCs, in 2013 European Conference on Circuit Theory and Design (ECCTD). 2013. pp. 1-4.
[14] Wenjuan Guo, H.Z., Nan Sun, A 13b-ENOB 173dB-FoM 2nd -Order NS SAR ADC with Passive Integrators, in 2017 Symposium on VLSI Circuits. 2017. pp. C236-C237.
[15] Yang, C., et al., An Area-Efficient SAR ADC With Mismatch Error Shaping Technique Achieving 102-dB SFDR 90.2-dB SNDR Over 20-kHz Bandwidth. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2021. 29(8): pp. 1575-1585.
[16] Seung-Yeob Baek, J.-K.L., Seung-Tak Ryu, An 88-dB Max-SFDR 12-bit SAR ADC With Speed-Enhanced ADEC and Dual Registers. IEEE Transactions on Circuits and Systems II: Express Briefs, 2013. 60(9): pp. 562-566.
[17] Huang, G.-Y., et al., A 10b 200MSs 0.82mW SAR ADC in 40nm CMOS, in 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC). 2013. pp. 289-292.
[18] Sekimoto, R., et al., A 0.5-V 5.2-fJ/Conversion-Step Full Asynchronous SAR ADC With Leakage Power Reduction Down to 650 pW by Boosted Self-Power Gating in 40-nm CMOS. IEEE Journal of Solid-State Circuits, 2013. 48(11): pp. 2628-2636.
[19] Kim, W., et al., A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC. IEEE Journal of Solid-State Circuits, 2016. 51(8): pp. 1826-1839.