鎖相迴路在許多系統中都會使用，較低頻段的鎖相迴路已有許多相關研究，架構也較為成熟。然而，近年來毫米波和兆赫波段的電路越來越受到關注，因此一個穩定的訊號源變得格外重要。毫米波段的訊號源主要問題是輸出功率不足，這導致無法滿足系統所需的最低功率要求。
因此，過去的研究中許多人使用III-V族製程或雙極性電晶體等非標準CMOS製程來解決這個問題。這些製程具有較高的最大震盪頻率和較好的功率處理能力，使其在毫米波電路中具有相當的優勢。然而，這些製程價格較高，且在系統整合時需要異質整合的技術。目前也有一些研究專注於使用標準CMOS製程來解決這個問題。這種製程更經濟實惠，並且在系統整合時不需要使用異質整合技術。
本論文主要旨在實現一個工作於兆赫波段的鎖相迴路，該鎖相迴路包含多個子電路實作，最終進行系統整合。整體系統使用了TSMC 40nm CMOS製程。本論文的研究工作分為三個主要部分，並進行了下線驗證。
在鎖相迴路中，震盪器是最關鍵的部分之一。在毫米波訊號源中，震盪器決定了輸出功率的大小。因此，該論文首先探討了震盪器的規格和設計流程。第一個設計是一個工作於295 GHz的壓控震盪器。該震盪器在1 MHz的相位雜訊為-79 dBc/Hz，輸出功率可達-9 dBm，消耗的直流功率為20 mW。在較低頻的鎖相迴路中，除頻器的設計通常相對較簡單。然而，在毫米波段，除頻器需要使用特殊的架構。本論文的第二個設計是一個工作於150 GHz的除二注入鎖定除頻器。當輸入功率為-10 dBm時，鎖定範圍可達11 GHz，消耗的直流功率僅為1.76 mW。第三個設計是一個工作於75 GHz的注入除三注入鎖定除頻器，其鎖定範圍達4 GHz，消耗的直流功率為2.8 mW。這些子電路的設計和實現對於整體鎖相迴路的運作至關重要。本論文的目標是實現一個可在兆赫波段工作的鎖相迴路，並通過所提出的設計和測試結果來驗證其性能。

Phase-locked loop (PLL) are widely used in many systems, and there have been extensive researches on PLL in lower frequency, making their architectures more mature. However, in recent years, circuits in the millimeter-wave and terahertz frequency have gained increasing attention, making a stable signal source even more crucial. The main challenge in the millimeter-wave frequency band is the insufficient output power, which fails to meet the minimum power requirements of the system.
In previous research, many have used non-standard CMOS processes such as III-V semiconductor processes or HBT to solve this issue. These processes offer higher maximum oscillation frequencies and better power handling capabilities, giving them a significant advantage in millimeter-wave circuits. However, these processes are more expensive and require heterogeneous integration techniques during system integration. There are also ongoing studies focusing on using standard CMOS process to solve this problem. Standard CMOS process is more cost-effective and do not require heterogeneous integration techniques during system integration.
The main objective of this thesis is to realize a millimeter-wave PLL. The PLL includes multiple sub-circuits that are implemented and integrated into the overall system using the TSMC 40nm CMOS process. The research work in this thesis is divided into three main parts and has been verified.
In a PLL, the oscillator is one of the most critical components. In millimeter-wave signal sources, the oscillator determines the output power. Therefore, the thesis first discusses the specifications and design process of the oscillator. The first design is a voltage-controlled oscillator (VCO) operating at 295 GHz. The VCO achieves a phase noise of -79 dBc/Hz at 1 MHz offset and an output power of -9 dBm, with a DC power consumption of 20 mW. In lower-frequency PLL, the design of dividers is usually relatively simple. However, at millimeter-wave frequency, divider requires special architectures. The second design in this thesis is a divide-by-2 injection-locked frequency divider operating at 150 GHz. It achieves a locking range of 11 GHz with an input power of -10 dBm and a DC power consumption of only 1.76 mW. The third design is a divide-by-3 injection-locked frequency divider operating at 75 GHz, with a locking range of 4 GHz and a DC power consumption of 2.8 mW. The design and implementation of these sub-circuits are crucial for the overall operation of the PLL. The goal of this thesis is to realize a PLL operating in the millimeter-wave frequency, and its performance is validated through the proposed designs and measurement results.

摘要 i
ABSTRACT ii
Contents iv
List of Figures vii
List of Tables xiii
Chapter 1 Introduction 1
1.1. Background 1
1.2. Organization 1
1.3. Voltage-controlled Oscillator 2
1.3.1 Oscillation condition 3
1.3.2 LC tank 5
1.3.3 Cross-coupled pair 10
1.3.4 Varactor 13
1.3.5 Phase noise 15
1.4. Phase-locked loop 18
1.4.1 Introduction of PLL 18
1.4.2 System model of CPPLL 19
Chapter 2 A 300-GHz transformer-based cross-coupled VCO with source degeneration technique in 40nm CMOS 22
2.1. Introduction 22
2.2. Transistor in millimeter-wave circuit 23
2.3. Output power in harmonic oscillator 26
2.4. Proposed topology 28
2.5. Design technique 29
2.5.1 Capacitive degeneration 30
2.5.2 Bulk frequency tuning 32
2.5.3 Transformer-based resonator 33
2.6. Design procedure 36
2.7. Simulation and measurement results 47
2.7.1 Simulation result 47
2.7.2 Measurement result 49
2.8. Comparison table and discussion 54
Chapter 3 Millimeter-wave frequency divider 59
3.1. Introduction 59
3.2. Injection-locked divider 60
3.2.1 Analysis of ILFD 61
3.2.2 Magnitude and phase condition 63
3.3. 150-GHz injection-locked frequency divider 65
3.3.1 Proposed topology 65
3.3.2 Transformer-based 4th order resonator 67
3.3.3 Design Procedure 73
3.3.4 Simulation and measurement result of 150-GHz ILFD 80
3.3.5 Comparison table and discussion 86
3.4. 75-GHz injection-locked frequency divider 88
3.4.1 Proposed topology 88
3.4.2 Analysis of divided-by-3 topology 88
3.4.3 Extra divided-by-2 injection 92
3.4.4 Simulation and measurement result of 75-GHz ILFD 94
3.4.5 Comparison table and discussion 98
Chapter 4 Integration of the phase-locked loop 102
4.1. System block diagram 102
4.2. Loop design 102
4.3. Chip implementation and simulation result 106
4.4. Comparison table and discussion 113
Chapter 5 Conclusion and Future Work 114
Reference 116

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