在現今通訊系統中，鎖相迴路作為時脈的輸出來源，嚴格的把控著收發端對於資料接收的的判斷時機，具有不可取代的地位。對於一時脈電路之評估，如參考時脈與鎖相迴路，我們需要其具高度精準且穩定的特性，同時亦須遵循著往低成本、小面積與低功耗的現今趨勢。
在過去的系統中，外來之參考時脈源較常被選擇於提供高效能之時脈，如石英振盪器或壓電振盪器等。然而此類振盪器皆有其各自的短版，如較高頻之石英振盪器難以整合於可攜式產品之上，壓電振盪器則須在高溫度穩定度與調頻性質間做取捨等。
近期本實驗室成功研發出一對於溫度、供應電壓與製程變異高度免疫之弛張振盪器，其原理為使用電壓平均回授的概念對頻率進行回授調整，並使用不同溫度係數電阻間的串並聯調整達成此振盪器高穩定之性質。此外，此電路使用穩壓器進一步穩定供應電壓值，並加入除頻器使其振盪之工作週期趨近於50%。
以上述弛張震盪器為參考時脈源，本次研究提出一個TSMC 0.18 μm 1P6M標準製程下，無額外元件振盪器之時脈系統。在原先44MHz之參考時脈下，此頻率合成器具有除32至除35之功能。為進一步最佳化系統之穩定時間與消耗面積等，一非線性相位頻率偵測器與一無精準電流源之自我修正電荷幫浦的架構被使用於此次研究中。最終此系統在溫度-20°C至80°C範圍內具有0.206%的最大變異量，而量測時因產生迴路輸出頻率不足的問題，因此對參考時脈進行降頻至32MHz以確保迴路正常運作。最終參考時脈抖動約為4.352ns的情況下，整體迴路輸出具有約127.9ps的抖動。

With an irreplaceable role of providing clock signals in modern systems such as communication systems, phase-locked loops (PLL) strictly control the timing for transceivers to exchange data. To ensure the systems perform well, we demand all the timing sources, including reference clocks and PLL’s, to be highly accurate and stable. Meanwhile, small circuit area, low cost and low power consumption are still considered as the trendy design issues.
In conventional electronic systems, external reference frequency generators are more commonly selected to provide timing signals with excellent properties. Devices such as crystal oscillators (XO) and MEMS oscillators are candidates for such a role, while each exhibits some inevitable shortage. The XO’s with higher frequency can hardly be integrated into portable products, and MEMS oscillators show trade-offs between temperature stability and tuning ability.
After years of dedication, an RC-based relaxation oscillator with high stability over temperature, supply voltage, and process variation had been successfully designed in our lab. The oscillator employed a voltage average feedback technique and the resistors of different temperature coefficients for series and shunt connections to achieve high thermal stability. In addition, a regulator was included to further stabilize the supply voltage, and a frequency divider was used to make the duty cycle of the output clock reach nearly 50%.
With a 44MHz relaxation oscillator acting as the on-chip reference frequency generator, this research proposes a PLL-based frequency synthesizer fabricated in TSMC 0.18μm 1P6M technology without any external timing device. This frequency synthesizer can be programmed within 32-35 dividing ratio. A nonlinear phase frequency detector and a self-calibrated charge pump without a precise current reference source are implemented to optimize the settling time and area usage, respectively. The measured maximum frequency variation across the temperature range from -20°C to 80°C is 0.206%. Due to the frequency drop issue of PLL when measuring, the reference clock frequency was lowered to 32MHz to ensure the loop worked normally. The jitter (rms) of the synthesizer output signal is roughly 127.9ps when the reference jitter is 4.352ns.

摘要
Abstract
致謝
目錄
圖目錄
表目錄
第一章 緒論------------------------------------------------1
1.1 研究背景------------------------------------------------1
1.2 研究動機------------------------------------------------3
1.3 論文章節架構--------------------------------------------5
第二章 鎖相迴路--------------------------------------------6
2.1 鎖相迴路簡介--------------------------------------------6
2.2 相位頻率偵測器------------------------------------------7
2.3 電荷幫浦------------------------------------------------8
2.4 壓控振盪器----------------------------------------------9
2.5 除頻器-------------------------------------------------10
2.6 迴路濾波器----------------------------------------------12
2.7 相位雜訊-----------------------------------------------13
2.8 頻域分析-----------------------------------------------15
2.8.1 系統性質分析------------------------------------------15
2.8.2 雜訊分析---------------------------------------------17
第三章 文獻回顧-------------------------------------------19
3.1 石英震盪器之電路整合------------------------------------19
3.2 MEMS振盪器之鎖相迴路整合--------------------------------22
3.3 原子鐘時脈整合------------------------------------------23
第四章 電路架構-------------------------------------------25
4.1 電路架構概述--------------------------------------------25
4.1.1 總電路架構說明----------------------------------------25
4.2 子電路-------------------------------------------------27
4.2.1 相位頻率偵測器(Phase Frequency Detector)--------------27
4.2.2 自我修正電荷幫浦(Self-Calibrated Charge Pump)---------28
4.2.3 壓控振盪器(Voltage-controlled Oscillator)-------------30
4.2.4 可調式除頻器(Programmable Divider)--------------------31
4.2.5 輸出緩衝電路(Output Buffer)---------------------------33
4.2.6 控制訊號電路(Control Signal Circuit)------------------34
4.3 電路工作順序--------------------------------------------34
第五章 模擬結果與晶片實現-----------------------------------36
5.1 子電路模擬結果-------------------------------------------36
5.1.1 相位頻率偵測器-----------------------------------------36
5.1.2 自我修正電荷幫浦---------------------------------------37
5.1.3 壓控振盪器---------------------------------------------38
5.1.4 可調式除頻器-------------------------------------------40
5.1.5 迴路控制訊號-------------------------------------------41
5.2 總體電路表現---------------------------------------------42
5.2.1 工作順序-----------------------------------------------42
5.2.2 抖動分析-----------------------------------------------44
5.2.3 頻譜圖-------------------------------------------------45
5.2.4 溫度變異度---------------------------------------------46
5.2.5 規格表-------------------------------------------------47
5.3 晶片布局考量---------------------------------------------48
第六章 量測結果---------------------------------------------50
6.1 PCB布局--------------------------------------------------50
6.2 量測儀器介紹---------------------------------------------51
6.3 量測說明-------------------------------------------------52
6.4 量測結果-------------------------------------------------54
6.4.1 波形展示-----------------------------------------------54
6.4.2 頻譜圖與相位雜訊----------------------------------------56
6.4.3 時脈抖動-----------------------------------------------58
6.4.4 除頻率驗證---------------------------------------------59
6.4.5 溫度穩定度---------------------------------------------60
6.5 問題討論-------------------------------------------------61
第七章 結論-------------------------------------------------63
7.1 結論-----------------------------------------------------63
7.2 規格比較-------------------------------------------------63
7.3 後續建議-------------------------------------------------65
7.3.1 低雜訊參考時脈------------------------------------------65
7.3.2 鎖相迴路-----------------------------------------------67
7.3.3 其他建議-----------------------------------------------68
參考文獻-----------------------------------------------------69

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