近年來，機器學習蓬勃發展，並逐漸充斥在我們的生活之中，而隨著其應用越來越廣，神經網路的模型也越來越複雜，然而，其龐大的運算量會導致其功耗較高，將神經網路的學習算法，實現於終端裝置變成一種挑戰。突波式神經網路模仿了生物大腦的特徵，利用突波來傳遞訊息，並使用了更接近生物表現，也更容易實現於硬體的學習算法，也因此，突波式神經網路被視為有極高的潛力，實現於未來低功耗的裝置當中。除此之外，生物神經的突波序列具有隨機性，而有文獻顯示此隨機性，能幫助基於仿生學習法的神經網路來完成學習。
本論文提出了一個，可重構並具隨機性與學習能力的突波式神經網路數位電路設計，其總共支援了256個仿生神經元與64k個突觸，以隨機突觸產生系統的隨機性，並具備兩種基於脈衝時序依賴可塑性的學習算法，此外，利用使用者定義連接，及輸入參數的調整，來將系統應用在不同的神經網路架構中，最後進行此系統，於實體設計後的面積、功率與延遲時間分析。

In recent years, machine learning has been growing rapidly, and our lives are gradually full of its applications. With an increasingly wider range of ML applications, the model of neural network becomes much more complex. However, it requires enormous amounts of calculations and consumes lots of power. This phenomenon makes implementing learning algorithms in neural networks on the edge devices become a challenging problem. To cope with this situation, researchers start to look into the spiking neural network (SNN), which imitates the characteristics of the human brain. It takes advantage of spikes to transmit information, and also apply a learning algorithm, whose functionality is not only closer to biological behaviors but also easier to be implemented in hardware. Therefore, the SNN is considered an essential part of future edge devices. Moreover, some literatures states that with the help of stochastic behavior in the spike trains, neural networks have better learning ability based on bio-inspired learning methods.
As a result, a reconfigurable and stochastic SNN digital hardware architecture with on-chip learning capability is proposed in this thesis. The system supports 256 leaky integrate-and-fire (LIF) neurons and 64k synapses, and generates stochastic behavior with stochastic synapses. It is also embedded with two learning rules using spike timing dependent plasticity (STDP). Furthermore, the system is able to be configured as different neural network architectures by user-defined connections and input parameters. Lastly, the physical design is completed, and the system area, power and latency are analyzed in this thesis.

第一章 緒論---------------------------------------1
1.1 研究動機與目標--------------------------------1
1.2 論文內容概述----------------------------------2
第二章 文獻回顧------------------------------------3
2.1 突波式神經網路簡介-----------------------------3
2.2 神經元模型與突觸模型簡介------------------------4
2.2.1 洩漏積分發射神經元----------------------------5
2.2.2 突觸模型-------------------------------------6
2.3 脈衝時序依賴可塑性應用於無監督式學習-------------6
2.4 相對差異學習法應用於循環突波式神經網路-----------7
2.5 隨機突觸之效用---------------------------------11
2.6 突波式神經網路之數位架構------------------------12
第三章 隨機突波式神經網路之軟體模擬------------------16
3.1 神經網路架構概述-------------------------------16
3.2 軟體模擬結果-----------------------------------20
3.2.1 數字圖片辨識模擬------------------------------20
3.2.2 數字圖片重建模擬------------------------------23
3.2.3 隨機突觸模擬---------------------------------26
第四章 隨機突波式神經網路之數位電路設計---------------28
4.1 系統架構---------------------------------------28
4.2 系統操作---------------------------------------30
4.3 序列周邊介面之輸入參數--------------------------33
4.4 神經元電路設計----------------------------------35
4.5 具學習能力之隨機突觸電路架構---------------------37
4.5.1 隨機突觸連接電路設計---------------------------37
4.5.2 脈衝時序依賴可塑性電路設計---------------------39
第五章 電路模擬結果與分析----------------------------42
5.1 循環突波式神經網路架構---------------------------42
5.1.1 架構簡介--------------------------------------42
5.1.2 模擬流程與結果--------------------------------44
5.2 前饋突波式神經網路架構---------------------------47
5.2.1 架構簡介--------------------------------------47
5.2.2 標籤化過程------------------------------------49
5.2.3 模擬流程與結果---------------------------------50
5.3 系統效能評估-------------------------------------53
第六章 結論與未來研究方向-----------------------------61
6.1 結論--------------------------------------------61
6.2 未來研究方向-------------------------------------62
參考文獻--------------------------------------------63

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