本論文的研究對象為1.2 kV和3.3 kV級之4H-SiC垂直功率元件，藉由量測找出具低特徵導通電阻(Specific on-resistance, Ron,sp)及高崩潰電壓的設計與元件。本論文研究的元件有四種，第一種為接面能障蕭基二極體(Junction Barrier Schottky Diode, JBS)，改變參數有電流擴散層濃度與JFET區域寬度；第二種為溝槽式金氧半能障蕭基二極體(Trench MOS Barrier Schottky Diode, TMBS)，改變參數有電流擴散層濃度、平台寬度、光罩設計、閘極氧化層製程及溝槽熱處理製程；第三種為垂直型雙佈植金氧半場效電晶體(Vertical Double Implanted MOSFET, VDMOS)，改變參數為P-well濃度與JFET區域寬度；第四種為溝槽式閘極金氧半場效電晶體(Trench gate MOSFET)，改變參數有電流擴散層濃度、P-well濃度、閘極氧化層製程及溝槽熱處理製程。
量測結果顯示1.2 kV級和3.3 kV級TMBS的Baliga品質因數最佳分別可達789 MW/cm2和1206 MW/cm2，其特徵導通電阻分別為2.14 mΩ-cm2和10.74 mΩ-cm2，崩潰電壓分別為1300 V和3600 V；1.2 kV級和3.3 kV級溝槽式閘極金氧半場效電晶體的Baliga品質因數最佳分別可達823 MW/cm2和1135 MW/cm2，其特徵導通電阻分別為1.99 mΩ-cm2和9.08 mΩ-cm2，崩潰電壓分別為1280 V和3210 V。

In this study, we investigate 1.2 kV and 3.3 kV class 4H-SiC vertical power devices. Through experiments, trenched devices with low specific on-resistance and high breakdown voltage are realized. The first part of this study is about Junction Barrier Schottky Diodes (JBS) with different current spreading layer (CSL) concentration and JFET region width. The second part is about Trench MOS Barrier Schottky Diodes (TMBS) with different CSL concentration, mesa width, layout design, oxide process and trench heat treatment. The third part is about Vertical Doubled Implanted MOSFET (VDMOS) with different JFET region width and P-well concentration. The fourth part is about trench gate MOSFET with different CSL concentration, P-well concentration, oxide process and trench heat treatment.
Measurement result shows that for TMBS, the best BFOM could reach 789 MW/cm2 and 1206 MW/cm2 for 1.2 kV and 3.3 kV devices, with Ron,sp of 2.14 mΩ-cm2 and 10.74 mΩ-cm2, breakdown voltage of 1300 V and 3600 V. For trench gate MOSFET, the best BFOM could reach 823 MW/cm2 and 1135 MW/cm2 for 1.2 kV and 3.3 kV devices, with Ron,sp of 1.99 mΩ-cm2 and 9.08 mΩ-cm2, breakdown voltage of 1280 V and 3210 V.

中文摘要-----------------------------------I
Abstract----------------------------------II
圖目錄-------------------------------------V
表目錄-------------------------------------VIII
第一章 序論---------------------------------1
1.1 研究動機--------------------------------1
1.2 碳化矽(SiC)材料簡介----------------------1
1.3 文獻回顧--------------------------------3
1.3.1 崩潰機制----------------------------3
1.3.2 漂移區(Drift Region)----------------3
1.3.3 Baliga’s Figure of Merit (BFOM)-----4
1.3.4 接面能障蕭基二極體--------------------4
1.3.5 溝槽式金氧半能障蕭基二極體-------------5
1.3.6 垂直型雙佈植金氧半場效電晶體-----------6
1.3.7 溝槽式閘極金氧半場效電晶體-------------7
1.4 論文大綱---------------------------------11
第二章 實驗與元件設計-------------------------12
2.1 磊晶參數---------------------------------12
2.2 元件製程與設計-JBS------------------------13
2.3 元件製程與設計-TMBS-----------------------15
2.4 元件製程與設計-VDMOS----------------------17
2.5 元件製程與設計-UMOS-----------------------19
2.6 實驗與量測方式----------------------------21
第三章 JBS-----------------------------------23
3.1 元件量測結果與分析-JFET寬度---------------23
3.2 元件量測結果與分析-CSL濃度----------------29
第四章 TMBS----------------------------------35
4.1 元件量測結果與分析-平台寬度----------------35
4.2 元件量測結果與分析-CSL濃度-----------------41
4.3 元件量測結果與分析-光罩設計----------------46
4.4 元件量測結果與分析-氧化層製程--------------51
4.5 元件量測結果與分析-溝槽熱處理--------------54
第五章 VDMOS---------------------------------57
5.1 元件量測結果與分析-JFET寬度---------------57
5.2 元件量測結果與分析-P-well濃度-------------62
第六章 UMOS----------------------------------67
6.1 元件量測結果與分析-CSL濃度----------------67
6.2 元件量測結果與分析-P-well濃度-------------74
6.3 元件量測結果與分析-氧化層製程--------------79
6.4 元件量測結果與分析-溝槽熱處理--------------81
第七章 結論----------------------------------84
7.1 結果分析與討論---------------------------84
7.2 未來展望---------------------------------87
參考文獻-------------------------------------88

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