對於CMOS-MEMS領域而言，薄膜擠壓阻尼效應(Squeeze-Film Damping Effect)為一項重要的物理效應，其在不同頻段上能夠產生出相異的阻尼效果來影響微結構之動態行為。本論文設計了六種不同結構之電容式感測器來探討此效應作用於其上的影響，結構設計方面使用有限元素分析軟體CoventorWare來進行各項效應參數的模擬，電路設計方面使用了三級的電路來將結構的機械訊號轉為電性訊號後增益並輸出，製程方面使用TSMC 2P4M 0.35μm CMOS標準製程來實現感測結構與電路的整合。
本研究晶片透過後製程之濕蝕刻流程蝕刻金屬犧牲層後釋放結構，後續進行反應離子蝕刻(RIE)來將晶片上方之保護層(Passivation)移除以完成整體結構之製作。量測方面分為三個部分進行分析，感測電路部分經由頻譜分析儀以及示波器驗證了實際電路規格與設計時的佈局後模擬十分相符；感測結構部分經由台灣半導體研究中心之雷射都卜勒光學量測儀觀察到了各結構之自然振頻與一大氣壓下的動態行為；整合系統部分經由工研院聲量實驗室的聲學系統量測到了感測器的單頻感測訊號並將其重組回系統之頻率響應，同時驗證了第一級電路之噪聲結果。上述實驗進行時遭遇了許多困難，而這些問題與現象將於後續的問題與討論小節中詳加說明。
本研究之感測器系統理論感測度為 ，聲學量測感測度於1kHz時為 ，各結構之第一級電路平坦區增益為 至 ，其等效輸出噪聲約為50μV/√Hz，此數值與佈局後模擬結果十分相近。

In the field of CMOS-MEMS, the Squeeze-Film Damping Effect is an important physical effect, which can produce different damping effects in different frequency bands to affect the dynamic behavior of microstructures. In this paper, six capacitive sensors with different structures are designed to explore the influence of this effect. In terms of structural design, the FEA software CoventorWare is used to simulate various parameters of this effect. The circuit design, a three-stage circuit is used to convert the mechanical signal of the structure into an electrical signal. In this research, we use the TSMC 2P4M 0.35μm CMOS standard process to realize the integration of the sensing structure and the circuit.
To the chips , the metal sacrificial layer was etched through the wet etching process to release the structure, and then by RIE removing the passivation layer above the chip, we complete the overall fabrication steps. The measurement is divided into three parts for analysis. First, the sensing circuit part is verified by the spectrum analyzer and oscilloscope. Second, the LDV observed the natural vibration frequency and the dynamic behavior under atmospheric pressure of each structure. Third, the integrated system is measured by the Calibration & Measurement LAB of ITRI. Many difficulties were encountered during the above experiments, and these problems will be explained in detail in the subsequent subsections. The theoretical sensitivity of the sensors in this study is , acoustic sensitivity is at 1kHz, the first-stage circuit flat-band gains of each structure are to , and their equivalent output referred noise are about 50μV/√Hz, which is very close to the post-simulation results.

摘要 I
ABSTRACT II
致謝 III
目錄 V
圖目錄 VIII
表目錄 XII
第 1 章 緒論 1
1-1 前言 1
(一) 微機電系統概述 2
(二) CMOS-MEMS概述 3
(三) 薄膜擠壓阻尼效應概述 4
1-2 文獻回顧 5
(一) 薄膜擠壓阻尼效應之發展 5
(二) 效應相關之CMOS-MEMS感測器研究 9
1-3 研究動機 10
第 2 章 薄膜擠壓阻尼效應之理論與模擬 12
2-1 薄膜擠壓阻尼效應之理論 12
(一) 非線性雷諾方程式 12
(二) 線性雷諾方程式 14
2-2 薄膜擠壓阻尼效應之模擬 19
(一) 相異面積平板模擬 19
(二) 相異孔洞設計模擬 22
第 3 章 感測結構之設計與驗證 26
3-1 結構感測度理論與模擬 26
(一) 相異彈簧結構搭配無孔洞平板之感測度比較 27
(二) 相同彈簧結構搭配相異平板設計之感測度比較 28
(三) 相同彈簧與孔洞規格，相異孔洞數量之感測度模擬 30
3-2 感測器結構之決定 33
(一) 結構設計 33
(二) 感測度、相位與頻寬 38
3-3 完整結構模型與後製程流程 40
第 4 章 感測電路之設計 45
4-1 感測電路設計 45
4-2 靜電吸附電壓 50
4-3 感測器總體感測度 51
第 5 章 量測結果與討論 53
5-1 感測器完整系統架構 53
5-2 感測電路量測 54
(一) 第一級電路頻譜分析儀量測結果 54
(二) 整體三級電路Transient行為量測結果 57
5-3 感測結構量測 59
(一) 結構釋放驗證 59
(二) 動態行為分析 62
5-4 整合系統量測 64
5-5 問題與討論 67
(一) 應力釋放造成的結構翹曲情形 67
(二) 濕蝕刻完成後之結構損壞 70
(三) 感測器理論感測度與模擬問題 72
第 6 章 結論與未來 74
6-1 研究成果與討論 74
6-2 未來工作 75
參考文獻 76

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